TMS320VC5420 datasheet(28/77 Pages) TI

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TMS320VC5420

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS080C – MARCH 1999 – REVISED APRIL 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA controller synchronization events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit

field of the DMA channel x sync select and frame count (DMSFCx) register selects the synchronization event

for a channel. The list of possible events and the DSYN values are shown in Table 5.

Table 5. DMA Synchronization Events

DSYN VALUE

DMA SYNCHRONIZATION EVENT

0000b

No synchronization used

0001b

McBSP0 Receive Event

0010b

McBSP0 Transmit Event

0011b

McBSP2 Receive Event

0100b

McBSP2 Transmit Event

0101b

McBSP1 Receive Event

0110b

McBSP1 Transmit Event

0111b

FIFO Receive Buffer Not Empty Event

1000b

FIFO Transmit Buffer Not Full Event

1001b – 1111b

Reserved

DMA channel interrupt selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, channels 0, 1, 2, and

3 are multiplexed with other interrupt sources. DMA channels 0 and 1 share an interrupt line with the receive

and transmit portions of McBSP2 (IMR/IFR bits 6 and 7), and DMA channels 2 and 3 share an interrupt line with

the receive and transmit portions of McBSP1 (IMR/IFR bits 10 and 11). When the ’5402 is reset, the interrupts

from these four DMA channels are deselected. The INTSEL bit field in the DMA channel priority and enable

control (DMPREC) register can be used to select these interrupts, as shown in Table 6.

Table 6. DMA Channel Interrupt Selection

INTSEL Value

IMR/IFR[6]

IMR/IFR[7]

IMR/IFR[10]

IMR/IFR[11]

00b (reset)

BRINT2

BXINT2

BRINT1

BXINT1

01b

BRINT2

BXINT2

DMAC2

DMAC3

10b

DMAC0

DMAC1

DMAC2

DMAC3

11b

Reserved

subsystem communications

The ’5420 device provides two options for efficient core-to-core communications:

D Core-to-core FIFO communications

D EMIF-to-HPI communications (asynchronous external memory interface-to host-port interface)

FIFO data communications

The subsystems’ FIFO communications interface is shown in the ’5420 functional block diagram (Figure 1). Two

unidirectional 8-word-deep FIFOs are available in the device for efficient interprocessor communication: one

configured for core A-to-core B data transfers, and the other configured for core B-to-core A data transfers. Each

subsystem, by way of DMA control, can write to its respective output data FIFO and read from its respective

input data FIFO. The FIFOs are accessed using the DMA’s I/O space, which is completely independent of the

CPU I/O space. The DMA transfers to or from the FIFOs can be synchronized to “receive FIFO not empty” and

“transmit FIFO not full” events providing protection from overflow and underflow. Subsystems can interrupt each

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