TMS320VC5420 datasheet(22/77 Pages) TI

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TMS320VC5420

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS080C – MARCH 1999 – REVISED APRIL 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programmable bank-switching

Programmable bank-switching can be used to insert one cycle automatically when crossing memory-bank

boundaries inside program memory or data memory space. One cycle can also be inserted when crossing from

program-memory space to data-memory space (’54x) or one program memory page to another program

memory page. This extra cycle allows memory devices to release the bus before other devices start driving the

bus; thereby avoiding bus contention. The size of the memory bank for the bank-switching is defined by the

bank-switching control register (BSCR). The BSCR of a particular DSP subsystem (A or B) is used for the

external memory interface depending on the logic level of the SELA/B pin.

BNKCMP

PS-DS

Reserved

IPIRQ

Reserved

EXIO

R/W

LEGEND: R = Read, W = Write

Figure 5. BSCR Register Bit Layout for Each DSP Subsystem

Table 4. BSCR Register Bit Functions for Each DSP Subsystem

BIT

NO.

BIT

NAME

RESET

VALUE

FUNCTION

15–12

BNKCMP

1111

Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four

MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared,

resulting in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

PS-DS

Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of

program read and data read or data read and program read.

PS-DS = 0

No extra cycles are inserted by this feature.

PS-DS = 1

One extra cycle is inserted between consecutive data and program reads.

10–9

Reserved

These bits are reserved and are unaffected by writes.

IPIRQ

The IPIRQ bit is used to send an interprocessor interrupt to the other subsystem. IPIRQ=1 sends the

interrupt. IPIRQ must be cleared before subsequent interrupts can be made. Refer to the interrupts section

for more details

7–3

Reserved

These bits are reserved and are unaffected by writes.

Bus holder. BH controls the data bus holder feature: BH is cleared to 0 at reset.

BH = 0

The bus holder is disabled.

BH = 1

The bus holder is enabled. When not driven, the data bus (PPD[15:0]) is held in the

previous logic level.

Reserved

These bits are reserved and are unaffected by writes.

EXIO

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

The external bus interface functions as usual.

EXIO = 1

The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the

HM bit of ST1 cannot be modified when the interface is disabled.

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