TMS370 datasheet(10/50 Pages) TI

10 / 50 page

TMS370Cx1x

8-BIT MICROCONTROLLER

SPNS012F – MAY 1987 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

program EPROM†

The TMS370C712 device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing

through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading

other internal memory. During programming, the EPROM is controlled by the EPROM control register (EPCTL).

The program EPROM module features include:

D Programming

–

In-circuit programming capability if VPP is applied to MC

–

Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 6.

D Write protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset: All programming to the EPROM module is halted

–

Low-power modes

–

13 V not applied to MC

program ROM†

The program ROM consists of 2K to 8K bytes of mask programmable read-only memory (see Table 7). The

program ROM is used for permanent storage of data or instructions. Programming of the mask ROM is

performed at the time of device fabrication.

Table 7. Program ROM Memory Map

’x11

’x10

’x12

ROM size

2K bytes

4K bytes

8K bytes

Memory mapped

7800h – 7FFFh

7000h – 7FFFh

6000h – 7FFFh

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx1x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

D Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

TMS370 Family

User’s Guide (literature number SPNU127) for more information.

D Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.

See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

D External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x1x device to reset external system components. Additionally, if a cold start (VCC is off

for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

† Memory addresses 7FF8h through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15

instructions are located between addresses 7FC0h and 7FDFh.

TMS370 Datasheet(PDF) 10 Page - Texas Instruments

TMS370 Datasheet(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL