TMS370 datasheet(27/50 Pages) TI

27 / 50 page

TMS370Cx1x

8-BIT MICROCONTROLLER

SPNS012F – MAY 1987 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial peripheral interface (continued)

The SPI block diagram is illustrated in Figure 11.

SPIBUF Buffer

SPIDAT

Data Register

SPIBUF.7-0

State Control

SPI CHAR

SPI BIT RATE

CLOCK POLARITY

SPI INT FLAG

SPICTL.6

SPIINT ENA

SPICTL.0

RECEIVER

OVERRUN

SPIDAT.7-0

SPICTL.1

TALK

SPICCR.2-0

SPICCR.5-3

System

Clock

SPICCR.6

SPICLK

MASTER/SLAVE†

SPICTL.7

Level 2 INT

SPIPRI.6

SPIPC2.7-4

SPISIMO

SPICTL.2

SPIPC1.3-0

SPISOMI

SPIPC2.3-0

Level 1 INT

† The diagram is shown in the slave mode.

Figure 11. SPI Block Diagram

instruction set overview

Table 17 provides an opcode to instruction cross reference of all 73 instructions and 274 opcodes of the

‘370Cx1x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode

while the numbers at the left side of the table represent the least significant nibble (LBN). The instruction of these

two opcode nibbles contains the mnemonic, operands, and byte / cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

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