TMS370 datasheet(14/50 Pages) TI

14 / 50 page

TMS370Cx1x

8-BIT MICROCONTROLLER

SPNS012F – MAY 1987 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write protection override (continued)

set to 1 to enter the nonprivileged mode, disabling write operations to specific configuration-control bits within

the PF. Table 10 displays the system-configuration bits which are write-protected during the nonprivileged mode

and must be configured by software prior to exiting the privileged mode.

Table 10. Privilege Bits

CONTROL BIT

NAME

LOCATION

CONTROL BIT

SCCRO

P010.6

OSC POWER

SCCR1

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN / IDLE

HALT / STANDBY

SPIPRI

P03F.5

P03F.6

P03F.7

SPI ESPEN

SPI PRIORITY

SPI STEST

T1PRI

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

† The privilege bits are shown in a bold typeface in the peripheral file

frame 1 section.

The write protect override (WPO) mode provides an external hardware method of overriding the write protection

registers (WPRs) of data EEPROM on the TMS370Cx1x. WPO mode is entered by applying a 12-V input to the

MC pin after the RESET pin input goes high (logic 1). The high voltage on the MC pin during the WPO mode

is not the programming voltage for the data EEPROM or Program EPROM. All EEPROM programming voltages

are generated on-chip. The WPO mode provides hardware system level capability to modify the content of data

EEPROM while the device remains in the application but only while requiring a 12 V external input on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx1x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, and Timer 1 remain active. System processing is suspended until a

qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected.

In the HALT mode (HALT / STANDBY = 1), the TMS370Cx1x is placed in its lowest power consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, or INT3) is

detected. The power-down mode-selection bits are summarized in Table 11.

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