TMS370 datasheet(13/50 Pages) TI

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TMS370Cx1x

8-BIT MICROCONTROLLER

SPNS012F – MAY 1987 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules.

Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt

mask and priority conditions.

The TMS370Cx1x has five hardware system interrupts (plus RESET) as shown in Table 9. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. A system interrupt may have multiple interrupt sources. All of the interrupt sources are

individually maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source

FLAG bit is individually readable for software polling or to determine which interrupt source generated the

associated system interrupt.

Two of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are

supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3

control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input

polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as

either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked

by the individual or global enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,

therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,

external interrupts INT2 and INT3 can be software configured as general purpose input / output pins if the

interrupt function is not required (INT1 can be similarly configured as an input pin).

Table 9. Hardware System Interrupts

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM

INTERRUPT

VECTOR

ADDRESS

PRIORITY†

External RESET

Watchdog Overflow

Oscillator Fault Detect

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

RESET‡

7FFEh, 7FFFh

External INT1

INT1 FLAG

INT1‡

7FFCh, 7FFDh

External INT2

INT2 FLAG

INT2‡

7FFAh, 7FFBh

External INT3

INT3 FLAG

INT3‡

7FF8h, 7FF9h

SPI Receiver (Rx) / Transmitter (Tx) Data

Complete

SPI INT FLAG

SPIINT

7FF6h, 7FF7h

Timer 1 Overflow

Timer 1 Compare 1

Timer 1 Compare 2

Timer 1 External Edge

Timer 1 Input Capture 1

Watchdog Overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

T1INT§

7FF4h, 7FF5h

† Relative priority within an interrupt level

‡ Release microcontroller from STANDBY and HALT low-power modes

§ Release microcontroller from STANDBY low-power mode

privileged operation and EEPROM write protection override

The TMS370Cx1x family is designed with significant flexibility to enable the designer to software-configure the

system and peripherals to meet the requirements of a variety of applications. The nonprivileged mode of

operation ensures the integrity of the system configuration, once it is defined for an application. Following a

hardware reset, the TMS370Cx1x operates in the privileged mode, where all peripheral file registers have

unrestricted read / write access, and the application program configures the system during the initialization

sequence following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is

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