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TMS370 Datasheet(PDF) 36 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 36 Page - Texas Instruments |
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36 / 50 page  TMS370Cx1x 8-BIT MICROCONTROLLER SPNS012F – MAY 1987 – REVISED FEBRUARY 1997 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 19. Peripheral File Frame Compilation (Continued) PF BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG P039 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 SPIDAT P03A to P03C Reserved P03D — — — — SPICLK DATA IN SPICLK DATA OUT SPICLK FUNCTION SPICLK DATA DIR SPIPC1 P03E SPISIMO DATA IN SPISIMO DATA OUT SPISIMO FUNCTION SPISIMO DATA DIR SPISOMI DATA IN SPISOMI DATA OUT SPISOMI FUNCTION SPISOMI DATA DIR SPIPC2 P03F SPI STEST SPI RIORITY SPI ESPEN — — — — — SPIPRI Timer1 Module Register Memory Map Modes: Dual-Compare and Capture / Compare P040 Bit 15 T1Counter MSbyte Bit 8 T1CNTR P041 Bit 7 T1 Counter LSbyte Bit 0 P042 Bit 15 Compare Register MSbyte Bit 8 T1C P043 Bit 7 Compare Register LSbyte Bit 0 P044 Bit 15 Capture/Compare Register MSbyte Bit 8 T1CC P045 Bit 7 Capture/Compare Register LSbyte Bit 0 P046 Bit 15 Watchdog Counter MSbyte Bit 8 WDCNTR P047 Bit 7 Watchdog Counter LSbyte Bit 0 P048 Bit 7 Watchdog Reset Key Bit 0 WDRST P049 WD OVRFL TAP SEL† WD INPUT SELECT2† WD INPUT SELECT1† WD INPUT SELECT0† — T1 INPUT SELECT2 T1 INPUT SELECT1 T1 INPUT SELECT0 T1CTL1 P04A WD OVRFL RST ENA† WD OVRFL INT ENA WD OVRFL INT FLAG T1 OVRFL INT ENA T1 OVRFL INT FLAG — — T1 SW RESET T1CTL2 Mode: Dual-Compare P04B T1EDGE INT FLAG T1C2 INT FLAG T1C1 INT FLAG — — T1EDGE INT ENA T1C2 INT ENA T1C1 INT ENA T1CTL3 P04C T1 MODE=0 T1C1 OUT ENA T1C2 OUT ENA T1C1 RST ENA T1CR OUT ENA T1EDGE POLARITY T1CR RST ENA T1EDGE DET ENA T1CTL4 Mode: Capture / Compare P04B T1EDGE INT FLAG — T1C1 INT FLAG — — T1EDGE INT ENA — T1C1 INT ENA T1CTL3 P04C T1 MODE = 1 T1C1 OUT ENA — T1C1 RST ENA — T1EDGE POLARITY — T1EDGE DET ENA T1CTL4 Modes: Dual-Compare and Capture / Compare P04D — — — — T1EVT DATA IN T1EVT DATA OUT T1EVT FUNCTION T1EVT DATA DIR T1PC1 P04E T1PWM DATA IN T1PWM DATA OUT T1PWM FUNCTION T1PWM DATA DIR T1IC/CR DATA IN T1IC/CR DATA OUT T1IC/CR FUNCTION T1IC/CR DATA DIR T1PC2 P04F T1 STEST T1 PRIORITY — — — — — — T1PRI † Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2 bits are ignored. |
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