TPS23754PWPR datasheet(27/41 Pages) TI

27 / 41 page

ADPTR_ON

PPDEN

PPD1

PPDEN

PPD

PPD2

18 V

1.55 V

= 32.26 k

1.55 V

5 A

3.01 k

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÷ ç

- m

PPDEN

ADPTR_ON

PPDEN

PPD1

PPD

PPD2

= V

+ R

= 18.07 V

(

)

(

)

PPDEN

PPDH

ADPTR_OFF

PPDEN

PPDH

PPD1

PPD

PPD2

+ R

= 14.54 V

(

)

RPPD

PPD1

PPD2

24 V

1.1

)

= 19.6 mW

+ R

3.01 k

+ 32.4 k

Setting Frequency (RFRS) and Synchronization

FRS

17250

(k ) =

= 69

(kHz)

250

FRS

47pF

Synchronization

Pulse

SYNC

1:1

1000pF

FRS

47pF

Synchronization

Pulse

SYNC

TPS23754

TPS23754-1

TPS23756

www.ti.com ....................................................................................................................................................... SLVS885B – OCTOBER 2008 – REVISED MAY 2009

2. Choose VADPTR-ON = 24 V × 0.75 = 18 V

3. Choose RPPD2 = 3.01 kΩ

4. Calculate RPPD1

Choose RPPD1 = 32.4 kΩ

5. Check PPD turn on and PPD turn off voltages

Voltages look acceptable.

6. Check PPD resistor power consumption.

Power is acceptable, but resistor values could be increased to reduce the power loss.

The converter switching frequency is set by connecting RFRS from the FRS pin to ARTN. The frequency may be

set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. Synchronization

at high duty cycles may become more difficult above 500 kHz due to the internal oscillator delays reducing the

available on-time. As an example:

1. Assume a desired switching frequency (fSW) of 250 kHz.

2. Compute RFRS:

Select 69.8 k

Ω.

The TPS23754 may be synchronized to an external clock to eliminate beat frequencies from a sampled system,

or to place emission spectrum away from an RF input frequency. Synchronization may be accomplished by

applying a short pulse (TSYNC) of magnitude VSYNC to FRS as shown in Figure 30. RFRS should be chosen so that

the maximum free-running frequency is just below the desired synchronization frequency. The synchronization

pulse terminates the potential on-time period, and the off-time period does not begin until the pulse terminates.

The pulse at the FRS pin should reach between 2.5 V and VB, with a minimum width of 22 ns (above 2.5 V) and

rise/fall times less than 10 ns. The FRS node should be protected from noise because it is high-impedance. An

RT on the order of 100 Ω in the isolated example reduces noise sensitivity and jitter.

Figure 30. Synchronization

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TPS23754PWPR Datasheet(PDF) 27 Page - Texas Instruments

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