TPS65192 datasheet(11/25 Pages) TI

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Channel

Control

VGH1

OUTx ToLCDPanel

VGL

RE1

INx

FLKx

FromTiming

Controller

RE2

VGH1

MIN

VG H1

= V

+ R

× R

+ R

´ ç

(1)

FLICKER CLOCKS

TPS65192

www.ti.com ....................................................................................................................................................................................................... SLVS962 – JULY 2009

Figure 19. Gate Voltage Shaping Timing Diagram

The alternative configuration shown in Figure 20 can be used to define a minimum gate voltage reached during

gate voltage shaping.

Figure 20. Alternative Gate Voltage Shaping Circuit Configuration

In this circuit, resistors RE1 and RE2 define both the rate of change of gate voltage decay and the minimum gate

voltage VMIN. Using the Thevenin equivalent, the operating parameters of Figure 20 are easily expressed as

follows:

The gate voltage shaping control logic in the TPS65192 allows the device to be used with one, two or three

flicker clock signals, according to the application requirements.

In 6-phase applications where one signal controls gate voltage shaping for six CLK channels, the flicker clock

should be connected to FLK1 and the unused pins FLK2 and FLK3 connected to GND.

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