TPS65192

Figure 26. Recommended Thermal Via Spacing

The thermal vias should make their connection to the bottom (or internal) copper plane with a complete

connection around the entire circumference of the plated through hole, and a ring of exposed copper (0.05mm

wide) around the vias at the bottom of the copper plane. It is not recommended to cover the vias with solder

mask as this can cause excessive voiding, and nor is it recommended to use a thermal relief web or spoke

connection as this impedes the conduction path to the other layers (see Figure 27).

Figure 27. Thermal Via Connection at the Bottom Layer

In any design, the copper areas used as heat sinks should be made as large as possible.

The power pad of the TPS65192 is electrically connected to VGL and therefore must not be connected to

the PCB’s ground plane.

For more detailed information concerning the thermal performance of QFN packages and recommendations

about how to mount the ICs on a PCB, refer to the following application reports:

SLOA122

QFN Layout Guidelines

SLUA271A

QFN/SON PCB Attachment

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Product Folder Link(s): TPS65192