IN1

IN2

IN3

IN4

IN5

IN6

IN1

IN2

IN3

IN4

IN5

IN6

TPS65192

In 6-phase applications where three signals control gate voltage shaping for six CLK channels, the flicker clock

for channels 1 and 4 should be connected to FLK1, the flicker clock for channels 2 and 5 connected to FLK2,

and the flicker clock for channels 3 and 6 connected to FLK3.

In 4-phase applications where two signals control gate voltage shaping for four CLK channels, the flicker clock

for phases 1 and 3 should be connected to FLK1, the flicker clock for phases 2 and 4 connected to FLK2, and

Alternatively, IN3 can be connected to IN2 and IN6 connected to IN5; this arrangement can simplify PCB layout.

Typical schematics for each of the above cases are included in the Applications section of this data sheet.

Gate voltage shaping is started by the falling edge of the FLK signal(s), which must occur during a valid part of

the clock waveform. For 6-phase systems, this means the last 60° of the clock waveform; for 4-phase systems,

this means the last 90° of the clock waveform (see Figure 21 and Figure 22). Falling edges of the FLK signal(s)

occurring outside the valid part of the clock waveform are ignored. The rising edge of the FLK signal(s) has no

effect, regardless of when it occurs.

Figure 21. FLK Falling Edge Validity, 6-Phase Applications

Figure 22. FLK Falling Edge Validity, 4-Phase Applications

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