APPLICATION INFORMATION

Power Supply Decoupling

PCB LAYOUT

TPS65192

For proper performance, it is recommended that each power supply rail be decoupled with high quality ceramic

decoupling capacitors placed as close to the IC supply pins as possible. The exact values used should be

optimized for each application, but a parallel combination of 10

µF and 100nF is a good place to start.

The output stages of the TPS65192 are capable of sinking and sourcing high peak currents – greater than

500mA in typical applications – and care must be taken during PCB layout to ensure that this performance can

be achieved in practice. In particular, the high rates of change of current occurring at the rising and falling edges

of each output require stray inductance to be minimized. This is most easily achieved by routing the output

signals using short, wide PCB tracks (as far as this is possible) and using a low impedance ground plane on the

other side of the board to conduct return currents. Tracks between the decoupling capacitors and the

corresponding power supply pins should also be kept short and wide as possible.

PCB layout must also be adequate from a thermal as well as electrical point of view. The TPS65192 is supplied

in a 28-pin QFN package designed to eliminate the need for heat sinks to dissipate the power generated in the

IC. The package, shown in Figure 25, is designed so that the lead-frame die pad is exposed on the bottom of the

IC, thereby providing an extremely low thermal resistance path between the die and the exterior of the package

Figure 25. Section View of a QFN Package

Copper areas in and on a PCB act as heat sinks for the QFN device; however, signal routing typically restricts

access to the power pad on the top layer of the PCB. In typical applications, therefore, the main copper area

used to conduct heat away from the IC is on the bottom layer.

TI recommends placing thermal vias in the solder mask defined thermal pad to transfer heat from the top layer of

the PCB to the inner or bottom layer used for heat sinking. The recommended via diameter is 0.3mm or less, and

via spacing 1mm (see Figure 26). For the 5 × 5 mm QFN package used for the TPS65192, five thermal vias are

typically used.

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Product Folder Link(s): TPS65192