TMC1175A datasheet(5/18 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC1175A

REV. 1.3.3 2/28/02

Pin Descriptions

Pin Name

Pin Number

Pin Type Pin Function Description

Inputs

VIN

RT – RB Analog Input. The input voltage conversion range lies between the

voltages applied to the RT and RB pins.

2.6V

Reference Voltage Top Input. RT is the top input to the reference

resistor ladder. A DC voltage applied to RT defines the positive end

of the VIN conversion range.

0.6V

Reference Voltage Bottom Input. RB is the bottom input to the

reference resistor ladder. A DC voltage applied to RB defines the

negative end of the VIN conversion range.

VR+

Reference Voltage Top Source. VR+ is the internal pull-up

reference resistor for self-bias operations.

VR–

Reference Voltage Bottom Source. VR- is the internal pull-down

reference resistor for self-bias operations.

CMOS

Output Enable. (CMOS-compatible) When LOW, D7-0 are enabled.

When HIGH, D7-0 are in a high-impedance state.

CONV

CMOS

Convert (Clock) Input. (CMOS-compatible) VIN is sampled on the

falling edge of CONV.

Outputs

D7-0

10–3

12–9,

7–4

CMOS/

TTL

Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible

digital outputs. Data is output following the rising edge of CONV.

Power

VDDA

14, 15, 18 17, 18,

+5V

Analog Supply Voltage. Independent +5 volt power connection to

analog comparator circuits.

VDDD

11, 13

13, 16

+5V

Digital Supply Voltage. Independent +5 volt power connection to

digital error correction and output drivers.

AGND

20, 21

24, 25

0.0V

Analog Ground. Connect to the system analog ground plane.

DGND

2, 24

3, 28

0.0V

Digital Ground. Connect to the system analog ground plane.

No Connect

N/C

1, 8, 15,

open

Not Connected.

Bandwidth Speciﬁcation Notes

The speciﬁcation for bandwidth of an A/D converter is some-

what different from the normal frequency-response speciﬁ-

cation used in ampliﬁers and ﬁlters. An understanding of the

differences will help in selecting converters properly for par-

ticular applications.

A/D conversion comprises two distinct processes: sampling

and quantizing. Sampling is “grabbing” a snapshot of the

input signal and holding it steady for quantizing. The quan-

tizing

process is approximating the analog input, which may

be any value within the conversion range, with its nearest

numerical value. While sampling is a high-frequency pro-

cess, quantizing operates on a dc signal, held steady by the

track/hold circuit. Therefore, the sampling process is what

relates to the dynamic characteristics of the converter.

Sampling involves an aperture time, the time during which

the track/hold is trying to capture the input signal and settle

on a dc value to hold. It is analogous to the shutter speed of a

camera: the shorter the aperture (or faster the shutter) the less

the signal will be blurred, and the less uncertainty there will

be in the quantized value.

For example, a 10 MHz sinewave with a 1V peak amplitude

(2Vp-p) has a maximum slew rate of 2

πfA at zero crossing,

or 62.8V/µs. With an 8-bit A/D converter, q (the quantization

step size) = 2V/255 = 7.8mV. The input signal will slew one

LSB in 124ps. To limit the error (and noise) contribution due

to aperture effects to 1/2LSB, the aperture must be shorter

than 62ps.

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