MX7705 datasheet(7/33 Pages) MAXIM

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Note 1: These errors are in the order of the conversion noise shown in Tables 1 and 3. This applies after calibration at the given

temperature.

Note 2: Recalibration at any temperature removes these drift errors.

Note 3: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar

and bipolar input ranges.

Note 4: Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar

input ranges.

Note 5: Gain error does not include zero-scale errors. It is calculated as (full-scale error - unipolar offset error) for unipolar ranges,

and (full-scale error - bipolar zero error) for bipolar ranges.

Note 6: Gain-error drift does not include unipolar offset drift or bipolar zero drift. Effectively, it is the drift of the part if only zero-

scale calibrations are performed.

Note 7: The analog input voltage range on AIN+ is given with respect to the voltage on AIN- on the MX7705.

Note 8: This common-mode voltage range is allowed, provided that the input voltage on analog inputs does not go more positive

than (VDD + 30mV) or more negative than (GND - 30mV). Parts are functional with voltages down to (GND - 200mV), but

with increased leakage at high temperature.

Note 9: The REF differential voltage, VREF, is the voltage on REF+ referenced to REF- (VREF = VREF+ - VREF-).

Note 10: Guaranteed by design.

Note 11: These calibration and span limits apply, provided that the absolute voltage on the analog inputs does not exceed (VDD +

30mV) or go more negative than (GND - 30mV). The offset calibration limit applies to both the unipolar zero point and the

bipolar zero point.

Note 12: When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the supply

current and power dissipation varies depending on the crystal or resonator type. Supply current is measured with the digi-

tal inputs connected to 0 or VDD, CLKIN connected to an external clock source, and CLKDIS = 1.

Note 13: If the external master clock continues to run in power-down mode, the power-down current typically increases to 67µA at

3V. When using a crystal or ceramic resonator across the CLKIN and CLKOUT as the clock source for the device, the

clock generator continues to run in power-down mode and the power dissipation depends on the crystal or resonator type

(see the

Power-Down Modes section).

Note 14: Measured at DC and applied in the selected passband. PSRR at 50Hz exceeds 120dB with filter notches of 25Hz or 50Hz.

PSRR at 60Hz exceeds 120dB with filter notches of 20Hz or 60Hz. PSRR depends on both gain and VDD.

Note 15: Provide fCLKIN whenever the MX7705 is not in power-down mode. If no clock is present, the device can draw higher than

specified current and can possibly become uncalibrated.

Note 16: All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.

GAIN

PSRR (dB)

(VDD = 5V)

PSRR (dB)

(VDD = 3V)

190

278

484

8 to 128

TIMING CHARACTERISTICS (continued)

(VDD = 3V or 5V, GND = 0, VREF+ = 1.225V for VDD = 3V and VREF+ = 2.5V for VDD = 5V, VREF- = GND, external fCLKIN =

2.4576MHz, CLKDIV bit = 0, CREF+ to GND = 0.1µF, CREF- to GND = 0.1µF, TA = TMIN to TMAX, unless otherwise noted.) (Note 16)

(Figures 8, 9)

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

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