Test Register

This register is reserved for factory testing of the device.

For proper operation of the MX7705, do not change this

register from its default power-on reset values.

Offset and Gain-Calibration Registers

The MX7705 contains one offset register and one gain

register for each input channel. Each register is 24 bits

wide and can be written and read. The offset registers

store the calibration coefficients resulting from a zero-

scale calibration, and the gain registers store the cali-

bration coefficients resulting from a full-scale

calibration. The data stored in these registers are 24-bit

straight binary values representing the offset or gain

errors associated with the selected channel. A 24-bit

read or write operation can be performed on the cali-

bration registers for any selected channel. During a

write operation, 24 bits of data must be written to the

register, or no data is transferred.

Write to the calibration registers in normal mode only.

After writing to the calibration registers, the devices

implement the new offset and gain-register calibration

coefficients at the beginning of a new acquisition. To

ensure the results are valid, discard the first conversion

result after writing to the calibration registers.

To ensure that a conversion is not made using invalid

calibration data, drive FSYNC high prior to writing to the

calibration registers, and then release FSYNC low to ini-

tiate conversion.

Power-On Reset

At power-up, the serial-interface, logic, digital-filter, and

modulator circuits are reset. The registers are set to

their default values. The device returns to wait for a

write to the communications register. For accurate

measurements, perform calibration routines after

power-up. Allow time for the external reference and

oscillator to start up before starting calibration. See the

Typical Operating Characteristics for typical external-

oscillator startup times.

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

______________________________________________________________________________________

25

Table 13. Output Data Rate and Notch Frequency vs. Filter Select and CLKIN Frequency

CLKIN FREQUENCY

CLK

FS1

FS0

OUTPUT DATA RATE

(FIRST NOTCH) (Hz)

-3dB FILTER CUTOFF**

(Hz)

1

0

0

0

20

5.24

1

0

0

1

25

6.55

1

0

1

0

100

26.20

1

0

1

1

200

52.40

2.4576

1

0

0

50

13.10

2.4576

1

0

1

60

15.70

2.4576

1

1

0

250

65.50

2.4576

1

1

1

500

131.00

*

These values are given for CLKDIV = 0. External clock frequency, fCLKIN, can be two times the values in this column if CLKDIV = 1.

**

The filter -3dB filter cutoff frequency = 0.262 x filter first-notch frequency.

Table 12. Clock Register

FIRST BIT (MSB)

(LSB)

FUNCTION

RESERVED

CLKOUT

DISABLE

CLOCK

DIVIDER

CLOCK

SELECT

FILTER SELECT

Name

MXID

ZERO

ZERO

CLKDIS

CLKDIV

CLK

FS1

FS0

Defaults

1

0

0

0

0

1

0

1