MX7705 datasheet(23/33 Pages) MAXIM

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ZERO: (Default = 0) Zero Bit. This is a read-only bit.

Values written to this bit are ignored.

CLKDIS: (Default = 0) Clock-Disable Bit. Set CLKDIS =

1 to disable the clock when using a crystal or resonator

across CLKIN and CLKOUT. Set CLKDIS = 1 to disable

CLKOUT when using a CMOS clock source at CLKIN.

CLKOUT is held low during clock disable to save

power. Set CLKDIS = 0 to allow other devices to use

the output signal on CLKOUT as a clock source and/or

to enable the external oscillator.

CLKDIV: (Default = 0) Clock-Divider Control Bit. The

MX7705 has an internal clock divider. Set this bit to 1 to

divide the input clock by two. When this bit is set to 0, the

MX7705 operates at the external oscillator frequency.

CLK: (Default = 1) Clock Bit. Set CLK = 1 for fCLKIN =

2.4576MHz with CLKDIV = 0, or 4.9152MHz with

CLKDIV = 1.

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

______________________________________________________________________________________

Table 6. Communications Register

FIRST BIT (MSB)

(LSB)

FUNCTION

COMMUNICATION

START/DATA READY

READ/WRITE

SELECT

POWER-DOWN

MODE

CHANNEL SELECT

Name

DRDY

RS2

RS1

RS0

CH1

CH0

Defaults

Table 7. Register Selection

RS2

RS1

RS0

POWER-ON RESET STATUS

Communications Register

0x00

Setup Register

0x01

Clock Register

0x05

Data Register

N/A

Test Register*

N/A

No Operation

—

Offset Register

0x1F 40 00

Gain Register

0x57 61 AB

Table 8. Channel Selection

CH1

CH0

AIN+

AIN-

OFFSET/GAIN

AIN1+

AIN1-

AIN2+

AIN2-

AIN1-

AIN2-

The test register is used for factory testing only.

Table 9. Setup Register

FIRST BIT (MSB)

(LSB)

FUNCTION

MODE CONTROL

PGA GAIN CONTROL

BIPOLAR/UNIPOLAR

MODE

BUFFER ENABLE

FSYNC

Name

MD1

MD0

B/U

BUF

FSYNC

Defaults

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