ADP1877ACPZ-R7 datasheet(14/32 Pages) AD

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ADP1877

Rev. 0 | Page 14 of 32

MODE OF OPERATION

The SYNC pin is a multifunctional pin. PWM mode is enabled

when SYNC is connected to VCCO or a high logic. With SYNC

connected to ground or left floating, pulse skip mode is enabled.

Switching SYNC from low to high or high to low on the fly

causes the controller to transition from forced PWM to pulse

skip mode or pulse skip mode to forced PWM, respectively, in two

clock cycles.

Table 5. Mode of Operation Truth Table

SYNC Pin

Mode of Operation

Low

Pulse skip mode

High

Forced PWM

No Connect

Pulse skip mode

Clock Signal

Forced PWM

The ADP1877 has a built-in pulse skip sensing circuitry that

allows the controller to skip PWM pulses, thus reducing the

switching frequency at light loads and, therefore, maintaining

high efficiency during a light load operation. The switching

frequency is a fraction of the natural oscillator frequency and is

automatically adjusted to regulate the output voltage. The

resulting output ripple is larger than that of the fixed frequency

forced PWM. Figure 25 shows that the ADP1877 operates in

PSM under a light load of 10 mA. Pulse skip frequency under a

certain light load is dependent on the inductor input and output

voltages.

CH3 20mV

CH2 200mV

CH1 10V

CH4 2A Ω

M200µs

A CH1

7.8V

SW1

COMP1 (CH2)

VOUT RIPPLE

INDUCTOR

CURRENT

Figure 25. Example of Pulse Skip Mode Under a Light 5 mA Load

When the output load is greater than the pulse skip threshold

current (when VCOMP reaches the threshold of 0.9 V), the

ADP1877 exits the pulse skip mode operation and enters the

fixed frequency discontinuous conduction mode (DCM), as

shown in Figure 26. When the load increases further, the

ADP1877 enters CCM.

CH3 20mV

CH2 5V

CH1 10V

CH4 2A Ω

M1µs

A CH1

13.4V

DH1

DL1

OUTPUT

RIPPLE

INDUCTOR CURRENT

Figure 26. Example of Discontinuous Conduction Mode (DCM) Waveform

In forced PWM, the ADP1877 always operates in CCM at any

load. The inductor current is always continuous (and even goes

negative when there is no load); thus, efficiency is poor at light

loads.

SYNCHRONIZATION

The switching frequency of the ADP1877 can be synchronized

to an external clock by connecting SYNC to a clock signal,

which should be between 1× and 2.3× of the internal oscillator

frequency, fOSC. The resulting switching frequency, fSW, is ½ of

the external SYNC frequency because the SYNC input is

divided by 2, and the resulting phases are used to clock the two

channels alternately. In synchronization, the ADP1877 operates

in PWM, and fSW equals ½ of fSYNC.

When an external clock is detected at the first SYNC edge, the

internal oscillator is reset, and the clock control shifts to SYNC.

The SYNC edges then trigger subsequent clocking of the PWM

outputs. The DH1/DH2 rising edges appear approximately 100 ns

after the corresponding SYNC edge, and the frequency is locked

to the external signal. Depending on the start-up conditions of

Channel 1 and Channel 2, either Channel 1 or Channel 2 can be

the first channel synchronized to the rising edge of the SYNC

clock. If the external SYNC signal disappears during operation,

the ADP1877 reverts to its internal oscillator. When the SYNC

function is used, it is recommended to connect a pull-up

resistor from SYNC to VCCO so that when the SYNC signal is

lost, the ADP1877 continues to operate in PWM.

SOFT START

The soft start period is set by an external capacitor between

SS1/SS2 and AGND. When EN1/EN2 is enabled, a current source

of 6.5 μA starts charging the capacitor, and the regulation voltage is

reached when the voltage at SS1/SS2 reaches 0.6 V. For more

information, see the Applications Information section.

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