ADP1877ACPZ-R7 datasheet(26/32 Pages) AD

26 / 32 page

ADP1877

Rev. 0 | Page 26 of 32

SWITCH NODE

The switch node is the noisiest place in the switcher circuit with

large ac and dc voltages and currents. This node should be wide

to keep resistive voltage drop down. To minimize the generation

of capacitively coupled noise, the total area should be small.

Place the FETs and inductor close together on a small copper

plane to minimize series resistance and keep the copper area small.

GATE DRIVER PATHS

Gate drive traces (DH and DL) handle high dI/dt and tend to

produce noise and ringing. They should be as short and direct

as possible. If possible, avoid using feedthrough vias in the gate

drive traces. If vias are needed, it is best to use two relatively

large ones in parallel to reduce the peak current density and the

current in each via. If the overall PCB layout is less than

optimal, slowing down the gate drive slightly can be very

helpful to reduce noise and ringing. It is occasionally helpful to

place small value resistors, such as between 2 Ω and 4 Ω, on the

DH and DL pins. These can be populated with 0 Ω resistors if

resistance is not needed. Note that the added gate resistance

increases the switching rise and fall times as well as switching

power loss in the MOSFET.

OUTPUT CAPACITORS

The negative terminal of the output filter capacitors should be

tied close to the source of the low side FET. Doing this helps to

minimize voltage differences between AGND and PGNDx.

ADP1877ACPZ-R7 Datasheet(PDF) 26 Page - Analog Devices