IMX35 datasheet(31/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.3

DPLL Electrical Specifications

There are three PLLs inside the i.MX35, all based on the same PLL design. The reference clock for these

PLLs is normally generated from an external 24-MHz crystal connected to an internal oscillator via

EXTAL24M and XTAL24 pins. It is also possible to connect an external 24-MHz clock directly to

EXTAL24M, bypassing the internal oscillator.

DPLL specifications are listed in Table 26.

4.9.4

Embedded Trace Macrocell (ETM) Electrical Specifications

ETM is an ARM protocol. The timing specifications in this section are given as a guide for a test point

access (TPA) that supports TRACECLK frequencies up to 133 MHz.

Figure 9 depicts the TRACECLK timings of ETM, and Table 27 lists the timing parameters.

Figure 9. ETM TRACECLK Timing Diagram

CS10

MISO hold time

tHmiso

5—

CS11

SPI_RDY setup time

tSDRY

5—

Table 26. DPLL Specifications

Parameter

Min.Typ.Max.

Unit

Comments

Reference clock frequency

100

MHz

Max. allowed reference clock phase noise

—

0.03

0.01

0.15

2 Tdck1

1 There are two PLL are used in the i.MX35, MPLL and PPLL. Both are based on same DPLL design.

Fmodulation < 50 kHz

50 kHz < Fmodulation 300 Hz

Fmodulation > 300 KHz

Frequency lock time (FOL mode or non-integer MF)

—

μs—

Phase lock time

—

100

μs—

Max. allowed PL voltage ripple

—

150

100

150

Fmodulation < 50 kHz

50 kHz < Fmodulation 300 Hz

Fmodulation > 300 KHz

Table 25. CSPI Interface Timing Parameters (continued)

Parameter

Symbol

Min.

Max.

Units

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