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IMX35 Datasheet(PDF) 81 Page - Freescale Semiconductor, Inc |
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IMX35 Datasheet(HTML) 81 Page - Freescale Semiconductor, Inc |
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81 / 148 page  i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 81 DI_DISPn_TIME_CONF_3 registers (n = 0,1,2). Figure 58 shows the timing of the parallel interface with read wait states. Figure 58. Parallel Interface Timing Diagram—Read Wait States 4.9.13.4.9 Parallel Interfaces, Electrical Characteristics Figure 59, Figure 61, Figure 60, and Figure 62 depict timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 54 lists the timing parameters at display access level. All WRITE OPERATION READ OPERATION DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISPB_D#_CS DISPB_RD DISPB_WR DISPB_PAR_RS DISPB_DATA DISPB_DATA DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 |
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