IMX35 datasheet(61/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.8

Fast Ethernet Controller (FEC) AC Electrical Specifications

This section describes the electrical information of the FEC module. The FEC is designed to support both

10- and 100-Mbps Ethernet networks. An external transceiver interface and transceiver function are

required to complete the interface to the media. The FEC supports the 10/100 Mbps Media Independent

Interface (MII) using a total of 18 pins. The 10-Mbps 7-wire interface that is restricted to a 10-Mbps data

rate uses seven of the MII pins for connection to an external Ethernet transceiver.

4.9.8.1

FEC AC Timing

This section describes the AC timing specifications of the FEC. The MII signals are compatible with

transceivers operating at a voltage of 3.3 V.

4.9.8.2

MII Receive Signal Timing

The MII receive timing signals consist of FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency

must exceed twice the FEC_RX_CLK frequency. Table 44 lists MII receive channel timings.

1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing when in 10 Mbps 7-wire interface mode.

Figure 40 shows the MII receive signal timings listed in Table 44.

Figure 40. MII Receive Signal Timing Diagram

Table 44. MII Receive Signal Timing

Num.

Characteristic1

Min.

Max.

Unit

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

—

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

—

FEC_RX_CLK pulse width high

35%

65%

FEC_RX_CLK period

FEC_RX_CLK pulse width low

35%

65%

FEC_RX_CLK period

FEC_RX_CLK (input)

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

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