IMX35 datasheet(54/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

NOTE

SDRAM CLK and DQS-related parameters are measured from the 50%

point—that is, “high” is defined as 50% of signal value and “low” is defined

as 50% of signal value. DDR SDRAM CLK parameters are measured at the

crossing point of SDCLK and SDCLK (inverted clock).

Test conditions are: Capacitance 15 pF for DDR PADS. Recommended

drive strength is Medium for SDCLK and High for Address and controls.

Figure 35. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 39. DDR2 SDRAM Read Cycle Parameter Table

PARAMETER

Symbol

DDR2-400

Unit

Min

Max

DDR24

DQS – DQ Skew (defines the Data valid window in

read cycles related to DQS).

tDQSQ

—0.35

DDR25

DQS DQ in HOLD time from DQS1

1The value was calculated for an SDCLK frequency of 133 MHz by the formula tQH = tHP – tQHS = min (tCL,tCH) – tQHS =

0.45

× tCK – tQHS = 0.45 × 7.5 – 0.45 = 2.925 ns.

tQH

2.925

—

DDR26

DQS output access time from SDCLK posedge

tDQSCK

–0.5

0.5

Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters1

1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

Parameter

Symbol

Min.

Max.

Unit

SD17

DQ and DQM setup time to DQS

tDS

0.95

—

SD18

DQ and DQM hold time to DQS

tDH

0.95

—

SD19

Write cycle DQS falling edge to SDCLK output delay time.

tDSS

1.8

—

SD20

Write cycle DQS falling edge to SDCLK output hold time.

tDSH

1.8

—

SDCLK

DQS (output)

DQ (output)

DQM (output)

Data

SD17

SD18

SD19

SD20

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