IMX35 datasheet(72/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.13.2

Interface to Sharp HR-TFT Panels

Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 53 lists the timing parameters. The

CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,

REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and

SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to

Table 52. Synchronous Display Interface Timing Parameters—Access Level

Parameter

Symbol

Min.

Typ.1

1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be device specific.

Max.

Units

IP16 Display interface clock low time

Tckl

Tdicd – Tdicu – 1.5

Tdicd2 –Tdicu3

2 Display interface clock down time

3 Display interface clock up time

where CEIL(X) rounds the elements of X to the nearest integers toward infinity.

Tdicd–Tdicu +1.5

IP17 Display interface clock high time

Tckh

Tdicp – Tdicd +

Tdicu – 1.5

Tdicp – Tdicd +

Tdicu

Tdicp–Tdicd +

Tdicu + 1.5

IP18 Data setup time

Tdsu

Tdicd – 3.5

Tdicu

—

IP19 Data holdup time

Tdhd

Tdicp – Tdicd – 3.5

Tdicp – Tdicu

—

IP20 Control signals setup time to

display interface clock

Tcsu

Tdicd – 3.5

Tdicu

—

Tdicd

---T

HSP_CLK

ceil

2 DISP3_IF_CLK_DOWN_WR

⋅

HSP_CLK_PERIOD

---------------------------------------------------------------------------------

⋅

Tdicu

---T

HSP_CLK

ceil

2 DISP3_IF_CLK_UP_WR

⋅

HSP_CLK_PERIOD

----------------------------------------------------------------------

⋅

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