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ICS8430002 Datasheet(PDF) 17 Page - Integrated Device Technology |
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ICS8430002 Datasheet(HTML) 17 Page - Integrated Device Technology |
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17 / 27 page ![]() ICS8430002AY REVISION C NOVEMBER 12, 2009 17 ©2009 Integrated Device Technology, Inc. ICS8430002 Data Sheet HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 6A to 6E show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 6A. PCLK/nPCLK Input Driven by an Open Collector CML Driver Figure 6C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver Figure 6E. PCLK/nPCLK Input Driven by an SSTL Driver Figure 6B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 6D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple PCLK nPCLK LVPECL Input CML 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V 3.3V R1 50 R2 50 R3 125 R4 125 R1 84 R2 84 3.3V Zo = 50 Ω Zo = 50 Ω PCLK nPCLK 3.3V 3.3V LVPECL LVPECL Input PCLK nPCLK LVPECL Input SSTL 2.5V Zo = 60 Ω Zo = 60 Ω 2.5V 3.3V R1 120 R2 120 R3 120 R4 120 LVPECL Input R3 84 R4 84 R1 125 R2 125 R5 100 - 200 R6 100 - 200 PCLK nPCLK 3.3V LVPECL 3.3V Zo = 50 Ω Zo = 50 Ω 3.3V 3.3V LVPECL Input C1 C2 |
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