ICS8430002 datasheet(3/27 Pages) IDT

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ICS8430002AY REVISION C NOVEMBER 12, 2009

ICS8430002 Data Sheet

HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER

Functional Description

NOTE: The functional description that follows describes the

operation using a 25MHz crystal or clock input. Valid PLL loop divider

values for different crystal or clock input frequencies are defined in

the Input Frequency Characteristics, Table 5, NOTE 1 and NOTE 2.

When a crystal is being used, there is no pre-divider therefore set P

= 1 when referencing all following equations on this page.

The ICS8430002 features a fully integrated PLL and therefore

requires no external components for setting the loop bandwidth. It

has a 2:1 multiplexer from which either a crystal input or a differential

input can be selected.

An external fundamental-mode quartz crystal can be used as the

input to the on-chip crystal oscillator. The range of allowable crystal

frequencies is 12MHz to 40MHz. When selected, the crystal

frequency is the reference frequency input to the phase detector. The

relationship between the VCO frequency, the crystal input frequency

and the M divider (M) is as follows:

A differential input clock can also be used. (See the Application

Information section for Wiring the Differential Input to Accept

Single-Ended Levels.) The differential input is followed by a

pre-divider that divides down the clock input frequency. This allows

an equal or lower reference frequency for the phase detector. See

Table 3C for available pre-divider values. The pre-divider value is set

through the P[2:0] pins or by using the serial programming interface.

The output frequency of the pre-divider is the reference frequency

input to the phase detector. The input frequency range of the phase

detector is 9MHz to 50MHz. The relationship between the VCO

frequency, the clock input frequency, the pre-divider (P) and the M

divider (M) is as follows:

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting the

VCO control voltage. The VCO of the PLL operates over a range of

490MHz to 650MHz. Note that for some values of M (either too high

or too low), the PLL will not achieve lock.

Using a 25MHz input, the M value integer-only range is shown in

Table 3B, Programmable VCO Frequency Table, P = ÷1. Valid M

values for which the PLL will achieve lock for a 25MHz reference are

defined as 19.6

≤ M ≤ 25.6. For different reference frequencies, the

range of valid M values may be calculated as follows:

The output of the VCO is scaled by output dividers prior to being sent

to each of the LVPECL output buffers. The output divider settings and

output frequency ranges are shown in table 3D.

Combining all the values of input frequency, pre-divider setting,

integer and fractional feedback divider settings, and output divider

setting, the output frequency may be calculated. The frequency out is

defined as follows:

The fractional-n M divider is composed of a 6-bit integer portion and

a 12-bit fractional portion. The decimal value obtained from these

settings can be determined as follows:

Where:MINT is the 6-bit integer portion

MFRAC is the 12-bit fractional portion

For a given required M divider, the value to program into the MFRAC

by 4096. For example, assuming a 25MHz crystal is being used, and

the desired VCO frequency is 515.625 (to support ethernet with

64B/66B encoding) the feedback setting required would be 20.625.

The integer portion of this number (20) is programed into the MINT

result (2560) is programmed into the MFRAC register. The full M

divider setting is then:

The frequency step size in ppm can be calculated using the following:

Substituting the combined equation

for the F terms in the

step size equation, the equation can be reduced to just the change in

M values.

Input Min (MHz)

Input Max (MHz)

Pre-Divider

950

÷1

100

÷2

200

÷4

250

÷5

400

÷8

144

800

÷16

225

800

÷25

288

800

÷32

FVCO

XTAL M

FVCO

FIN

-------- M

490MHz

FIN P

⁄

---------------------- M 650MHz

FIN P

⁄

----------------------

≤≤

FOUT

FVCO

--------------

FIN

-------- M

-----

MMINT

MFRAC

4096

------------------

20 2560

4096

------------

20.625

stepsize

F0 F1

–

-----------------

ppm

FIN

-------- M

-----

stepsize

M0 M1

–

---------------------

×10

ppm

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