ATA8201 datasheet(18/44 Pages) ATMEL

18 / 44 page

4971C–INDCO–04/09

ATA8201/ATA8202

3.1

Pin CLK_OUT

Pin CLK_OUT is an output to clock a connected microcontroller. The clock is available in

Stand by a nd Active m odes. Th e frequ ency f

CL K_ OU T can b e a d justed via the pins

CLK_OUT_CTRL0 and CLK_OUT_CTRL1, and is calculated as follows:

The signal at CLK_OUT output has a nominal 50% duty cycle. To save current, it is recom-

mended that CLK_OUT be switched off during Standby mode.

3.2

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry is derived from one clock. As seen in Figure 3-2 on

page 17, this clock cycle, T

DCLK, is derived from the crystal oscillator (XTO) in combination with a

divider.

DCLK controls the following application relevant parameters:

- Debouncing of the data signal stream

- Start-up time of the RX signal path

The start-up time and the debounce characteristic depend on the selected bit rate range

(BR_Range) which is defined by pins BR0 and BR1. The clock cycle T

XDCLK is defined by the fol-

lowing formulas for further reference:

BR_Range

⇒

BR_Range 0: T

XDCLK = 8 × TDCLK

BR_Range 1: T

XDCLK = 4 × TDCLK

BR_Range 2: T

XDCLK = 2 × TDCLK

BR_Range 3: T

XDCLK = 1 × TDCLK

Table 3-2.

Setting of f

CLK_OUT

CLK_OUT_CTRL1

CLK_OUT_CTRL0

Function

Clock on pin CLK_OUT is switched off

(Low level on pin CLK_OUT)

fCLK_OUT =fXTO /3

fCLK_OUT =fXTO /6

fCLK_OUT =fXTO /12

DCLK

XTO

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