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ATmega324P Datasheet(PDF) 131 Page - ATMEL Corporation |
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ATmega324P Datasheet(HTML) 131 Page - ATMEL Corporation |
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131 / 377 page ![]() 131 7674F–AVR–09/09 ATmega164P/324P/644P Figure 14-12. Timer/Counter Timing Diagram, no Prescaling Figure 14-13 shows the same timing data, but with the prescaler enabled. Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8) 14.11 Register Description 14.11.1 TCCR1A – Timer/Counter1 Control Register A • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk Tn (clk I/O/1) clk I/O TOVn(FPWM) and ICF n(if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7 6 5 4 3210 (0x80) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0000 |
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