ATmega324P datasheet(133/377 Pages) ATMEL

133 / 377 page

133

7674F–AVR–09/09

ATmega164P/324P/644P

Table 14-4 on page 133 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to

the phase correct or the phase and frequency correct, PWM mode.

Note:

1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See

“Phase Correct PWM Mode” on page 125. for more details.

• Bit 1:0 – WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-5 on page 134. Modes of operation supported by the

Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,

and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page

122.).

Table 14-4.

Compare Output Mode, Phase Correct and Phase and Frequency Correct

PWM

(1)

COMnA1/COMnB1

COMnA0/COMnB0

Description

Normal port operation, OCnA/OCnB disconnected.

WGMn3:0 = 9 or 11: Toggle OCnA on Compare

Match, OCnB disconnected (normal port operation).

For all other WGM1 settings, normal port operation,

OC1A/OC1B disconnected.

Clear OCnA/OCnB on Compare Match when

up-counting. Set OCnA/OCnB on Compare Match

when downcounting.

Set OCnA/OCnB on Compare Match when

up-counting. Clear OCnA/OCnB on Compare Match

when downcounting.

ATmega324P Datasheet(PDF) 133 Page - ATMEL Corporation