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ATmega324P Datasheet(PDF) 135 Page - ATMEL Corporation |
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ATmega324P Datasheet(HTML) 135 Page - ATMEL Corporation |
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135 / 377 page ![]() 135 7674F–AVR–09/09 ATmega164P/324P/644P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description. • Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 14-10 and Figure 14-11. If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 14.11.3 TCCR1C – Timer/Counter1 Control Register C • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCRnA is written when operating in a PWM mode. When writing a logical one to the FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit. The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. Table 14-6. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source (Timer/Counter stopped). 001 clk I/O/1 (No prescaling) 010 clkI/O/8 (From prescaler) 011 clk I/O/64 (From prescaler) 100 clk I/O/256 (From prescaler) 101 clkI/O/1024 (From prescaler) 1 1 0 External clock source on Tn pin. Clock on falling edge. 1 1 1 External clock source on Tn pin. Clock on rising edge. Bit 765 4 3 2 1 0 (0x82) FOC1A FOC1B – – – – – – TCCR1C Read/Write R/W R/W R R R R R R Initial Value000 0 0 0 0 0 |
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