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9128D–RKE–01/09

ATA5749 [Preliminary]

6.2

Programming

The configuration register is programmed serially using the SPI bus, starting with the MSB. It

consists of the Enable line (EN), the Data line (SDIN_TXDIN), and the SPI-Bus Clock (SCK).

The SDIN_TXDIN data is loaded on the positive edge of the SCK. The contents of the configura-

tion register become programmed on the negative SCK edge of the last bit (LSB) of the

programming sequence. The timing of this bus is shown in Figure 6-1. Note that the maximum

usable clock speed on the SPI bus is limited to 2 MHz.

Figure 6-1.

SPI Bus Timing

At the conclusion of the 32 bit programming sequence, the SDIN_TXDIN line becomes the mod-

ulation input for the RF transmitter. After programming is complete, the SCK signal has no effect

on the device. To disable the transmitter and enter the OFF Mode, EN and SDIN_TXDIN must

be returned to the LOW state. For clarity, several additional timing diagrams are included. Figure

6-2 shows the situation when the programming terminates faster then the XTO is ready.

Figure 6-2.

Timing Diagram if Register Programming is Faster than

ΔT

XTO

T

Setup

T

EN_setup

T

SCK_Low

T

SCK_High

T

SCK_Cycle

T

SDIN_TXDIN_setup

T

Hold

SDIN_TXDIN

SCK

X

X

MSB-1

MSB

EN

ΔT

XTO

T

PLL

X

X

X

FSK;

TX_Mode2

ASK:

TX_Mode1 and

TX_Mode2

TX-Data

OFF_

Mode

OFF_Mode

TX_

Mode1

Start_Up_

Mode_2

Start_Up_

Mode_1

32-bit Configuration

CLK (Output)

SCK (Input)

EN (Input)

PA (Output

Power)

SDIN_TXDIN

(Input)