CONFIG0

The CONFIG0 register holds a bit mask for sockets and

domains that are enabled for polling as well as a

polling delay (minimum delay between sets of polls)

and features enable/disable bits. Table 2 shows the

various options for CONFIG0.

The optional polling delay (bits 2:0) inserts after polling

the set of all sockets and domains that are enabled in

bits 15:8 with a minimal pause of 2.5ms between PECI

reads. After polling all enabled sockets and domains,

the device pauses PECI communications for the config-

ured time before starting to poll the set of enabled

sockets and domains again. Table 3 shows the various

polling delay options.

CONFIG1

The CONFIG1 register configures the maximum num-

ber of retries before aborting a PECI temperature read

as well as the originated (suggested) PECI bit time.

Table 4 shows the various options for CONFIG1.

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7

BIT(S)

DESCRIPTION

DEFAULT

15:8

Polling enable for sockets and domains

00h

15

1 = enable socket 3, domain 1

0

14

1 = enable socket 3, domain 0

0

13

1 = enable socket 2, domain 1

0

12

1 = enable socket 2, domain 0

0

11

1 = enable socket 1, domain 1

0

10

1 = enable socket 1, domain 0

0

9

1 = enable socket 0, domain 1

0

8

1 = enable socket 0, domain 0

0

7

0 = disable timeout

1

6

1 = alternate data representation

0 = 16-bit data representation

0

5

(PEC) on device return data

0 = disable PEC

1

4

1 = mask temperature alerts

0 = activate alerts

0

3

Reserved, set to 0

0

2:0

Poll delay, see Table 3

5

Table 2. CONFIG0 Register

POLL DELAY VALUE

DELAY BETWEEN POLLS (ms)

0

Polling on request only

1

2.5

25

310

450

5

100 (default)

6

500

7

Reserved

Table 3. Polling Delay

BIT(S)

DESCRIPTION

DEFAULT

15:8

Originated PECI bit time

(before negotiation)

01h: RESERVED

14h…0FFh: CONFIG1[15:8] + 1μs

Minimum: 14h (= 21μs/47.62kHz)

Maximum: 0FFh (= 256μs/3.906kHz)

02h

7:0

Maximum number of retries for PECI

transactions

03h

Table 4. CONFIG1 Register