ADE7858ACPZ datasheet(42/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 42 of 76

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VAGAIN

IRMS

VRMS

Power

Apparent

Average

(38)

The output is scaled by –50% by writing 0xC00000 to the VA

gain registers and increased by +50% by writing 0x400000 to

them. These registers can be used to calibrate the apparent

power (or energy) calculation in the ADE7858 for each phase.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits. Similar to

registers presented in Figure 15, AVAGAIN, BVAGAIN,

CVAGAIN 24-bit registers are accessed as 32-bit registers with 4

most significant bits padded with 0s and sign extended to 28

bits.

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation register

to calibrate and eliminate the dc component in the rms value

(see the Root Mean Square Measurement section). The voltage

and current rms values are then multiplied together in the

apparent power signal processing. As no additional offsets are

created in the multiplication of the rms values, there is no specific

offset compensation in the apparent power signal processing. The

offset compensation of the apparent power measurement in each

phase should be done by calibrating each individual rms

measurement.

Apparent Power Calculation using VNOM

The ADE7858 may compute the apparent power multiplying

the phase rms current by an rms voltage introduced externally

in VNOM[23:0] 24-bit signed register. When one of bits 13, 12,

11 (VNOMCEN, VNOMBEN, VNOMAEN) in

COMPMODE[15:0] register is set to 1, the apparent power in

the corresponding phase (phase x for VNOMxEN, x=A,B,C) is

computed in this way. When bits VNOMxEN are cleared to 0,

the default value, then the arithmetic apparent power is

computed.

VNOM[23:0] register contains a number determined by U, the

desired rms voltage and

, the rms value of the phase

voltage when the ADC inputs are at full scale:

400

191

VNOM

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(39)

Usually U is the nominal phase rms voltage.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. Similar to the register presented in Figure

16, VNOM 24-bit signed register is accessed as a 32-bit register

with 8 most significant bits padded with 0s.

Apparent Energy Calculation

Apparent energy is defined as the integral of apparent power.

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ergy

ApparentEn

)

(

(40)

Similar to active and reactive powers, the ADE7858 achieves

the integration of the apparent power signal in two stages (see

Figure 47). The first stage is done inside the DSP: every 125μsec

(8KHz frequency), the instantaneous phase apparent power is

accumulated into an internal register. When a threshold is

reached, a pulse is generated at processor port and the

threshold is subtracted from the internal register. The second

stage is done outside the DSP and consists in accumulating the

pulses generated by the processor into internal 32-bit

accumulation registers. The content of these registers is

transferred to va-hr registers xVAHR[31:0], x=A, B, C when

these registers are accessed.

Figure 42 from the Active Energy Calculation section explains

this process. The VATHR[47:0] 48-bit register contains the

threshold. Its value depends on how much energy is assigned to

1LSB of VA-hour registers. Let’s suppose a derivative of VAh

[10n VAh], n an integer, is desired as 1LSB of VAHR. Then

VATHR may be computed using the following expression:

3600

PMAX

VATHR

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where:

PMAX=33,516,139=0x1FF6A6B, the instantaneous power

computed when the ADC inputs are at full scale.

fs=8KHz is the frequency with which the DSP computes the

instantaneous power.

UFS, IFS are the rms values of phase voltages and currents when

the ADC inputs are at full scale.

The VATHR[47:0] is a 48-bit register. As previously stated, the

serial ports of the ADE7858 work on 32, 16 or 8-bit words.

Similar to the WTHR[47:0] register presented in Figure 43,

VATHR[47:0] is accessed as two 32-bit registers

(VATHR1[31:0] and VATHR0[31:0]), each having 8 most

significant bits padded with 0s.

This discrete time accumulation or summation is equivalent to

integration in continuous time following the description in

expression (41).

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Lim

ergy

ApparentEn

(41)

where:

is the discrete time sample number.

is the sample period.

In the ADE7858, the phase apparent powers are accumulated in

AVAHR[31:0], BVAHR[31:0] and CVAHR[31:0] 32-bit signed

registers. The apparent energy register content can roll over to

full-scale negative (0x80000000) and continue increasing in

value when the apparent power is positive. Conversely, if

because of offset compensation in rms data path, the apparent

power is negative, the energy register would underflow to full-

scale positive (0x7FFFFFFF) and continue decreasing in value.

ADE7858ACPZ Datasheet(PDF) 42 Page - Analog Devices

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