ADE7858ACPZ datasheet(63/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 63 of 76

Table 25. HPFDIS register (address 0x43B6)

Bit

Location

Bit

Mnemonic

Default

value

Description

23:0

00000000

When HPFDIS=0x00000000, then all high pass filters in voltage and current channels are enabled.

When the register is set to any non zero value, all high pass filters are disabled.

Table 26. IPEAK register (address 0xE500)

Bit Location

Bit Mnemonic

Default value

Description

23-0

IPEAKVAL[23:0]

These bits contain the peak value determined in the current channel.

IPPHASE[0]

When this bit is set to 1, phase A current generated IPEAKVAL[23:0] value.

IPPHASE[1]

When this bit is set to 1, phase B current generated IPEAKVAL[23:0] value.

IPPHASE[2]

When this bit is set to 1, phase C current generated IPEAKVAL[23:0] value.

31-27

00000

These bits are always 0.

Table 27. VPEAK register (address 0xE501)

Bit Location

Bit Mnemonic

Default value

Description

23-0

VPEAKVAL[23:0]

These bits contain the peak value determined in the voltage channel.

VPPHASE[0]

When this bit is set to 1, phase A voltage generated VPEAKVAL[23:0] value.

VPPHASE[1]

When this bit is set to 1, phase B voltage generated VPEAKVAL[23:0] value.

VPPHASE[2]

When this bit is set to 1, phase C voltage generated VPEAKVAL[23:0] value.

31-27

00000

These bits are always 0.

Table 28. STATUS0 register (address 0xE502)

Bit

Location

Bit

Mnemonic

Default

value

Description

AEHF

When this bit is set to 1, it indicates that bit 30 of any one of the total active energy registers

AWATTHR, BWATTHR, CWATTHR has changed.

Reserved

This bit is always set to 0.

REHF

When this bit is set to 1, it indicates that bit 30 of any one of the total reactive energy registers

AVARHR, BVARHR, CVARHR has changed.

Reserved

This bit is always set to 0.

VAEHF

When this bit is set to 1, it indicates that bit 30 of any one of the apparent energy registers AVAHR,

BVAHR, CVAHR has changed.

LENERGY

When this bit is set to 1, in line energy accumulation mode, it indicates the end of an integration

over an integer number of half line cycles set in LINECYC[15:0] register.

REVAPA

When this bit is set to 1, it indicates that the phase A total active power has changed sign. The sign

itself is indicated in bit 0 (AWSIGN) of PHSIGN[15:0] register (see Table 38).

REVAPB

When this bit is set to 1, it indicates that the phase B total active power has changed sign. The sign

itself is indicated in bit 1 (BWSIGN) of PHSIGN[15:0] register (see Table 38).

REVAPC

When this bit is set to 1, it indicates that the phase C total active power has changed sign. The sign

itself is indicated in bit 2 (CWSIGN) of PHSIGN[15:0] register (see Table 38).

REVPSUM1

When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data path has

changed sign. The sign itself is indicated in bit 3 (SUM1SIGN) of PHSIGN[15:0] register (see Table 38).

REVRPA

When this bit is set to 1, it indicates that the phase A total reactive power has changed sign. The

sign itself is indicated in bit 4 (AVARSIGN) of PHSIGN[15:0] register (see Table 38).

REVRPB

When this bit is set to 1, it indicates that the phase B total reactive power has changed sign. The sign

itself is indicated in bit 5 (BVARSIGN) of PHSIGN[15:0] register (see Table 38).

REVRPC

When this bit is set to 1, it indicates that the phase C total reactive power has changed sign. The sign

itself is indicated in bit 6 (CVARSIGN) of PHSIGN[15:0] register (see Table 38).

REVPSUM2

When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data path has

changed sign. The sign itself is indicated in bit 7 (SUM2SIGN) of PHSIGN[15:0] register (see Table 38).

CF1

When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin, that is an active

low pulse has been generated. The bit is set even if the CF1 output is disabled by setting bit 9

(CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is determined by bits

2-0 (CF1SEL) in CFMODE[15:0] register (see Table 36).

CF2

When this bit is set to 1, it indicates a high to low transition has occurred at CF2 pin, that is an active

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