Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADE7858ACPZ Datasheet(PDF) 65 Page - Analog Devices

Part # ADE7858ACPZ
Description  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADE7858ACPZ Datasheet(HTML) 65 Page - Analog Devices

Back Button ADE7858ACPZ Datasheet HTML 61Page - Analog Devices ADE7858ACPZ Datasheet HTML 62Page - Analog Devices ADE7858ACPZ Datasheet HTML 63Page - Analog Devices ADE7858ACPZ Datasheet HTML 64Page - Analog Devices ADE7858ACPZ Datasheet HTML 65Page - Analog Devices ADE7858ACPZ Datasheet HTML 66Page - Analog Devices ADE7858ACPZ Datasheet HTML 67Page - Analog Devices ADE7858ACPZ Datasheet HTML 68Page - Analog Devices ADE7858ACPZ Datasheet HTML 69Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 65 / 76 page
background image
Preliminary Technical Data
ADE7858
Rev. PrA | Page 65 of 76
Bit
Location
Bit
Mnemonic
Default
value
Description
24
PKV
0
When this bit is set to 1, it indicates that the period used to detect the peak value in the voltage
channel has ended. VPEAK[31:0] register contains the peak value and the phase where the peak has
been detected (see Table 27).
31:25
Reserved
000
0000
Reserved. These bits are always 0.
Table 30. MASK0 register (address 0xE50A)
Bit
Location
Bit
Mnemonic
Default
value
Description
0
AEHF
0
When this bit is set to 1, it enables an interrupt when bit 30 of any one of the total active energy
registers AWATTHR, BWATTHR, CWATTHR changes.
1
Reserved
0
This bit does not manage any functionality.
2
REHF
0
When this bit is set to 1, it enables an interrupt when bit 30 of any one of the total reactive energy
registers AVARHR, BVARHR, CVARHR changes.
3
Reserved
0
This bit does not manage any functionality.
4
VAEHF
0
When this bit is set to 1, it enables an interrupt when bit 30 of any one of the apparent energy
registers AVAHR, BVAHR, CVAHR changes.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it enables an interrupt at the end of an
integration over an integer number of half line cycles set in LINECYC[15:0] register.
6
REVAPA
0
When this bit is set to 1, it enables an interrupt when the phase A total active power changes sign.
7
REVAPB
0
When this bit is set to 1, it enables an interrupt when the phase B total active power changes sign.
8
REVAPC
0
When this bit is set to 1, it enables an interrupt when the phase C total active power changes sign.
9
REVPSUM1
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF1 data
path changes sign.
10
REVRPA
0
When this bit is set to 1, it enables an interrupt when the phase A total reactive power changes sign.
11
REVRPB
0
When this bit is set to 1, it enables an interrupt when the phase B total reactive power changes sign.
12
REVRPC
0
When this bit is set to 1, it enables an interrupt when the phase C total reactive power changes sign.
13
REVPSUM2
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF2 data
path changes sign.
14
CF1
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF1 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF1 output is disabled
by setting bit 9 (CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is
determined by bits 2-0 (CF1SEL) in CFMODE[15:0] register (see Table 36).
15
CF2
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF2 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF2 output is disabled
by setting bit 10 (CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is
determined by bits 5-3 (CF2SEL) in CFMODE[15:0] register (see Table 36).
16
CF3
When this bit is set to 1, it enables an interrupt when a high to low transition occurs at CF3 pin, that
is an active low pulse is generated. The interrupt may be enabled even if the CF3 output is disabled
by setting bit 11 (CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is
determined by bits 8-6 (CF3SEL) in CFMODE[15:0] register (see Table 36).
17
DREADY
0
When this bit is set to 1, it enables an interrupt when all periodical (at 8KHz rate) DSP computations
finish.
18
REVPSUM3
0
When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3 data
path changes sign.
31-19
Reserved
00 0000
0000
0000
Reserved. These bits do not manage any functionality.
Table 31. MASK1 register (address 0xE50B)
Bit
Location
Bit
Mnemonic
Default
value
Description
0
NLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition
based on total active and reactive powers.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com