ADE7858ACPZ datasheet(27/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 27 of 76

a number of half line cycles. The phase where this event took

place is identified in bits 14, 13, 12 (VSPHASE[2:0]) of

PHSTATUS[15:0] register. This condition is illustrated in Figure

30.

PHASE A VOLTAGE

FULL SCALE

SAGLVL[23:0]

SAGCYC[7:0]=0x4

Bit 16 (SAG) in

STATUS1[31:0]

VSPHASE[0]=

PHSTATUS[12]

IRQ1\ pin

FULL SCALE

SAGLVL[23:0]

SAGCYC[7:0]=0x4

PHASE B VOLTAGE

VSPHASE[1]=

PHSTATUS[13]

STATUS[16] and

PHSTATUS[13] set to 1

STATUS1[16] and

PHSTATUS[12] cancelled

by a write to

STATUS1[31:0] with SAG

bit set

Figure 30. ADE7858 Sag Detection

Figure 30 shows phase A voltage falling below a threshold that

is set in the sag level register (SAGLVL[23:0]) for four half line

cycles (SAGCYC=4). When bit 16 (SAG) in STATUS1[31:0]

PHSTATUS[15:0] register also is set to 1 because the event

happened on phase A. Bit 16 (SAG) in STATUS1[31:0] register

and all bits 14,13,12 (VSPHASE[2:0]) of PHSTATUS[15:0]

STATUS1[31:0] register with SAG bit set to 1. The

SAGCYC[7:0] register represents the number of half line cycles

the phase voltage must remain below the level indicated in

SAGLVL register in order to trigger a sag condition. 0 is not

valid a valid number for SAGCYC. For example, when the sag

cycle (SAGCYC[7:0]) contains 0x07, the SAG flag in

STATUS1[31:0] register is set at the end of the seventh half line

cycle for which the line voltage falls below the threshold. If bit

16 (SAG) in MASK1[31:0] is set,

IRQ interrupt pin is driven

low in case of a sag event in the same moment the status bit 16

(SAG) in STATUS1[31:0] register is set to 1. The SAG status bit

in STATUS1[31:0] register and all bits 14, 13, 12

(VSPHASE[2:0]) of PHSTATUS[15:0] register are cleared and

IRQ pin is set back high by writing STATUS1[31:0] register

with the status bit set to 1.

When the phase B voltage falls below the threshold indicated

into SAGLVL[23:0] register for two line cycles, bit VSPHASE[1]

in PHSTATUS[15:0] register is set to 1 and bit VSPHASE[0] is

cleared to 0. In the same moment, bit 16 (SAG) in

STATUS1[31:0] register is set to 1 to indicate the condition.

Note that the internal zero-crossing counter is always active. By

setting SAGLVL[23:0] register, the first sag detection result is,

therefore, not done across a full SAGCYC period. Writing to

the SAGCYC[7:0] register when the SAGLVL[23:0] is already

initialized resets the zero-crossing counter, thus ensuring that

the first sag detection result is obtained across a full SAGCYC

period.

The recommended procedure to manage sag events is the

following:

-enable SAG interrupts in MASK1[31:0] register by setting bit

16 (SAG) to 1.

-when a sag event happens, the

IRQ

interrupt pin goes low and

bit 16 (SAG) in STATUS1[31:0] is set to 1.

-STATUS1[31:0] register is read with bit 16 (SAG) set to 1.

-PHSTATUS[15:0] is read, identifying on which phase or

phases a sag event happened.

-STATUS1[31:0] register is written with bit 16 (SAG) set to 1. In

this moment, bit SAG and all bits 14,13,12 (VSPHASE[2:0]) of

PHSTATUS[15:0] register are erased.

Sag Level Set

The content of the sag level register SAGLVL[23:0] is compared

to the absolute value of the output from HPF. Writing 5,928,256

(0x5A7540) to SAGLVL register, puts the sag detection level at

full scale – see Voltage Channel ADC Chapter, so the sag event

is triggered continuously. Writing 0x00 or 0x01 puts the sag

detection level at 0, so the sag event is never triggered.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. Similar to the register presented in Figure

16, SAGLVL register is accessed as 32-bit registers with 8 most

significant bits padded with 0s.

Peak Detection

The ADE7858 records the maximum absolute values reached

by the voltage and current channels over a certain number of

half line cycles and stores them into the less significant 24 bits

of VPEAK[31:0] and IPEAK[31:0] 32-bit registers.

PEAKCYC[7:0] register contains the number of half line cycles

used as a time base for the measurement. The circuit uses the

zero crossing points identified by the zero crossing detection

circuit. Bits 4, 3, 2 (PEAKSEL[2:0]) in MMODE[7:0] register

select on which phases the peak measurement is done. Bit 2

selects phase A, bit 3 selects phase B and bit 4 selects phase C.

Selecting more than one phase to monitor the peak values

decreases proportionally the measurement period indicated in

PEAKCYC[7:0] register because zero crossings from more

phases are involved in the process. When a new peak value is

determined, one of bits 26, 25, 24 (IPPHASE[2:0] or

VPPHASE[2:0]) in IPEAK[31:0] and VPEAK[31:0] registers is

set to 1 identifying the phase that triggered the peak detection

event. For example, if a peak value has been identified on phase

A current, bit 24 (IPPHASE[0]) in IPEAK[31:0] register is set to

1. If next time a new peak value is measured on phase B, then

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