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ADE7858ACPZ Datasheet(PDF) 66 Page - Analog Devices

Part # ADE7858ACPZ
Description  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADE7858ACPZ Datasheet(HTML) 66 Page - Analog Devices

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ADE7858
Preliminary Technical Data
Rev. PrA| Page 66 of 76
Bit
Location
Bit
Mnemonic
Default
value
Description
1
Reserved
0
This bit does not manage any functionality.
2
VANLOAD
0
When this bit is set to 1, it enables an interrupt when at least one phase enters no-load condition
based on apparent power.
3
ZXTOVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase A voltage misses.
4
ZXTOVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase B voltage misses.
5
ZXTOVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase C voltage misses.
6
ZXTOIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase A current misses.
7
ZXTOIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase B current is missing.
8
ZXTOIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing on phase C current is missing.
9
ZXVA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A voltage.
10
ZXVB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B voltage.
11
ZXVC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C voltage.
12
ZXIA
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase A current.
13
ZXIB
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase B current.
14
ZXIC
0
When this bit is set to 1, it enables an interrupt when a zero crossing is detected on phase C current.
15
RSTDONE
0
Because the RSTDONE interrupt cannot be disabled, this bit does not have any functionality
attached. It can be set to 1 or cleared to 0 without having any effect.
16
SAG
0
When this bit is set to 1, it enables an interrupt when a SAG event occurs on one of the phases
indicated by bits 14-12 (VSPHASE) in PHSTATUS[15:0] register (see Table 32).
17
OI
0
When this bit is set to 1, it enables an interrupt when an overcurrent event occurs on one of the
phases indicated by bits 5-3 (OIPHASE) in PHSTATUS[15:0] register (see Table 32).
18
OV
0
When this bit is set to 1, it enables an interrupt when an overvoltage event occurs on one of the
phases indicated by bits 11-9 (OVPHASE) in PHSTATUS[15:0] register (see Table 32).
19
SEQERR
0
When this bit is set to 1, it enables an interrupt when a negative to positive zero crossing on phase
A voltage is not followed by a negative to positive zero crossing on phase B voltage, but by a
negative to positive zero crossing on phase C voltage.
20,22,21
Reserved
00
Reserved. These bits do not manage any functionality.
23
PKI
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the current channel has ended.
24
PKV
0
When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in
the voltage channel has ended.
31:25
Reserved
000 0000
Reserved. These bits do not manage any functionality.
Table 32. PHSTATUS register (address 0xE600)
Bit Location
Bit Mnemonic
Default value
Description
2-0
Reserved
000
Reserved . These bits are always 0.
3
OIPHASE[0]
0
When this bit is set to 1, phase A current generated bit 17 (OI) in STATUS1[31:0]
4
OIPHASE[1]
0
When this bit is set to 1, phase B current generated bit 17 (OI) in STATUS1[31:0]
5
OIPHASE[2]
0
When this bit is set to 1, phase C current generated bit 17 (OI) in STATUS1[31:0]
8-6
Reserved
000
Reserved. These bits are always 0.
9
OVPHASE[0]
0
When this bit is set to 1, phase A voltage generated bit 18 (OV) in STATUS1[31:0]
10
OVPHASE[1]
0
When this bit is set to 1, phase B voltage generated bit 18 (OV) in STATUS1[31:0]
11
OVPHASE[2]
0
When this bit is set to 1, phase C voltage generated bit 18 (OV) in STATUS1[31:0]
12
VSPHASE[0]
0
When this bit is set to 1, phase A voltage generated bit 16 (SAG) in STATUS1[31:0]
13
VSPHASE[1]
0
When this bit is set to 1, phase B voltage generated 16 (SAG) in STATUS1[31:0]
14
VSPHASE[2]
0
When this bit is set to 1, phase C voltage generated 16 (SAG) in STATUS1[31:0]
15
Reserved
0
Reserved . This bit is always 0.
Table 33. PHNOLOAD register (address 0xE608)
Bit
Location
Bit
Mnemonic
Default
value
Description
0
NLPHASE[0]
0
-0: phase A is out of no-load condition based on total active/reactive powers.
-1: phase A is in no load condition based on total active/reactive powers. Bit set together with



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