ADE7858ACPZ datasheet(47/76 Pages) AD

47 / 76 page

Preliminary Technical Data

ADE7858

Rev. PrA | Page 47 of 76

When VARACC[1:0]=10, the reactive powers are accumulated

depending on the sign of corresponding active power. If the

active power is positive, the reactive power is accumulated as is.

If the active power is negative, the sign of the reactive power is

changed for accumulation. Figure 55 presents the way the sign

adjusted reactive power accumulation mode works. Note that in

this mode, the var-hr registers continue to accumulate reactive

powers in signed mode, even if the CF pulses are generated

based on the sign adjusted accumulation mode.

REVRPx bit

in STATUS0

xVARSIGN bit

in PHSIGN

ACTIVE

POWER

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

REACTIVE

ENERGY

NO-LOAD

THRESHOLD

NO-LOAD

THRESHOLD

REACTIVE

POWER

POS

VARNOLOAD

SIGN=POSITIVE

NEG

POS

Figure 55. Reactive power accumulation in sign adjusted mode

Sign of sum of phase powers in CFx data path

The ADE7858 has a sign detection circuitry for the sum of

phase powers that are used in CFx, x=1, 2, 3 data path. As seen

in the beginning of Energy to Frequency Conversion chapter,

the energy accumulation in CFx data path is executed in two

stages. Every time a sign change is detected in the energy

accumulation at the end of the first stage, that is after the energy

accumulated into the 55 bit accumulator reaches one of

WTHR[47:0], VARTHR[47:0 or VATHR[47:0] thresholds, a

dedicated interrupt may be triggered synchronously with the

corresponding CF pulse. The sign of each sum may be read in

PHSIGN[15:0] register.

Bits 18, 13, 9 (REVPSUM3, REVPSUM2, and respectively

REVPSUM1) of STATUS0[31:0] register are set to 1 when a sign

change of the sum of powers in CF3, CF2 or CF1 data paths

occurs. To correlate these events with the pulses generated at

CFx pins, after a sign change occurs, bits REVPSUM3,

REVPSUM2 and REVPSUM1 are set in the same moment in

which a high to low transition at CF3, CF2 and respectively CF1

pin occurs.

Bits 8, 7, 3 (SUM3SIGN, SUM2SIGN and respectively

SUM1SIGN) of PHSIGN[15:0] register are set in the same

moment with bits REVPSUM3, REVPSUM2 and REVPSUM1

and indicate the sign of the sum of phase powers. When cleared

to 0, the sum is positive. When set to 1, the sum is negative.

Interrupts attached to the bits 18, 13, 9 (REVPSUM3,

REVPSUM2, and respectively REVPSUM1) in STATUS0[31:0]

MASK0[31:0] register. If enabled, the

IRQ pin is set low and

the status bit is set to 1 whenever a change of sign occurs. To

find the phase that triggered the interrupt, PHSIGN[15:0]

the status bit is cleared and

IRQ pin is set back high by writing

STATUS0 register with the corresponding bit set to 1.

NO-LOAD CONDITION

The no-load condition is defined in metering equipment

standards as occurring when the voltage is applied to the meter

and no current flows in the current circuit. To eliminate any

creep effects in the meter, the ADE7858 contains two separate

no-load detection circuits: one related to the total active and

reactive powers and one related to the apparent powers.

No-load detection based on total active and reactive

powers

This no-load condition is triggered when the absolute values of

both phase total active and reactive powers are less than or

equal to positive thresholds indicated in APNOLOAD[23:0]

and respective VARNOLOAD[23:0] signed 24-bit registers. In

this case, the total active and reactive energies of that phase are

not accumulated and no CF pulses are generated based on these

energies. APNOLOAD[23:0] represents the positive no-load

level of active power relative to PMAX, the maximum active

power obtained when full scale voltages and currents are

provided at ADC inputs. VARNOLOAD[23:0] represents the

positive no-load level of reactive power relative to PMAX. The

expression used to compute APNOLOAD[23:0] signed 24-bit

value is:

PMAX

APNOLOAD

noload





(44)

where: PMAX=33,516,139=0x1FF6A6B, the instantaneous

power computed when the ADC inputs are at full scale

UFS, IFS, the rms values of phase voltages and currents when the

ADC inputs are at full scale.

Un, the nominal rms value of phase voltage.

ADE7858ACPZ Datasheet(PDF) 47 Page - Analog Devices

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