Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

Setup Time for CS to WR,RD

Clock Width

(Figure 3)

3V

¾

500

600

¾

ns

Hold Time for CS to WR,RD

Clock Width

(Figure 3)

3V

¾

50

100

¾

ns

¾

VDD drop down to 0V

20

¾¾

ms

¾¾

0.05

¾¾

V/ms

Note:

1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal

Power-on Reset (POR) circuit will not operate normally.

2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions

of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for

20ms (min.) before rising to the normal operating voltage.

HT1620

Rev. 1.80

7

July 27, 2009

PATENTED

9 0 %

5 0 %

1 0 %

G N D

W R , R D

C l o c k

Figure 1

5 0 %

V A L I D D A T A

5 0 %

D B

W R , R D

C l o c k

G N D

G N D

Figure 2

C S

G N D

5 0 %

5 0 %

F I R S T

C l o c k

L A S T

C l o c k

G N D

W R , R D

C l o c k

Figure 3

V D D

0 V

Figure 4. Power-on Reset Timing