ST7093 datasheet(6/43 Pages) SITRONIX

6 / 43 page

ST7093

Ver 2.1

6/43

2003/09/23

PIIN

N D

RIIP

TIIO

NAME

I/O Interfaced

FUNCTION

MPU

Select registers.

0: Instruction register (for write)

address counter (for read)

1: Data register (for write and read)

RW_WR

MPU

Select read or write.

In 68 mode

In 80 mode

0: Write

1: Read

1: Not active

E_RD

MPU

Starts data read/write.

In 68 mode

In 80 mode

0: Not active

0: Read

1: Enable

1: Not active

DB4 to DB7

I/O

MPU

Four high order bi-directional tristate data bus

pins. Used for data transfer and receive

between the MPU and the ST7093. In serial interface mode

DB7 is SI (input data), DB6 is SCL (serial clock).

DB0 to DB3

I/O

MPU

Four low order bi-directional tristate data bus

pins. Used for data transfer and receive

between the MPU and the ST7093.

These pins are not used during 4-bit operation. (Fixed high)

CSB

MPU

Chip select signal. Active low.

RESETB

MPU

Reset signal. Active low.

MPU

External clock input pin. it must be fixed to “Vss” , when the

internal oscillator circuit is used. In case of the external clock

mode, CK is used as the clock and OS bit should be turn off.

MPU

Interface selection

0: 80 mode interface

1: 68 mode interface

DIRS

MPU

SEG direction selection

0: SEG1

SEG80

1: SEG80

SEG1

MPU

Interface selection valid when PS=1

0: 4 bit bus mode

1: 8 bit bus mode

MPU

Interface selection

0: serial mode

1: 4bit/ 8bit bus mode

COM1 to

COM24

COMI1,COMI2

LCD

Common signals. COMI1 and COMI2 are the same signal

SEG1 to SEG80

LCD

Segment signals

CAP1+, CAP1-

CAP2+, CAP2-

Capacitor connection pins for voltage booster

Vout

I/O

Voltage booster output pin

Voltage adjust pin between V0 and VSS

REF

MPU

Reference voltage selection pin

0: internal regulator is selected

1: external reference voltage input to Vext

Vext

I/O

External reference voltage input

V0 to V4

Power supply

Power supply for LCD drive

V0 - Vss = 7 V (Max)

VDD , GND

Power supply

VDD : 2.4V to 3.6V, GND: 0V

Test 0 to Test3

Test pin. open

Note: 1. V0>=V1>=V2>=V3>=V4>=VSS must be maintained

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