ADE7878ACPZ datasheet(57/92 Pages) AD

57 / 92 page

ADE7878

Rev. 0 | Page 57 of 92

The derivative of wh must be chosen in such a way to obtain a

CFxDEN register content greater than 1. If CFxDEN = 1, then

the CFx pin stays active low for only 1 μs; therefore, avoid this

number. The frequency converter cannot accommodate fractional

results; the result of the division must be rounded to the nearest

integer. If CFxDEN is set equal to 0, then the ADE7878 considers it

to be equal to 1.

The pulse output for all digital-to-frequency converters stays

low for 80 ms if the pulse period is larger than 160 ms (6.25

Hz). If the pulse period is smaller than 160 ms and CFxDEN is

an even number, the duty cycle of the pulse output is exactly

50%. If the pulse period is smaller than 160 ms and CFxDEN is

an odd number, the duty cycle of the pulse output is

(1+1/CFxDEN) × 50%

The pulse output is active low and preferably connected to an

LED, as shown in Figure 70.

Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the

CFMODE[15:0] register decide if the frequency converter

output is generated at the CF3, CF2, or CF1 pin. When

Bit CFxDIS is set to 1 (the default value), the CFx pin is disabled

and the pin stays high. When Bit CFxDIS is cleared to 0, the

correspondent CFx pin output generates an active low signal.

Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask Register

MASK0[31:0] manage the CF3, CF2, and CF1 related

interrupts. When the CFx bits are set (whenever a high to low

transition at the corresponding frequency converter output

occurs), an interrupt IRQ0 is triggered and a status bit in the

STATUS0[31:0] register is set to 1. The interrupt is available

even if the CFx output is not enabled by the CFxDIS bits in the

CFMODE[15:0] register.

VDD

CFx PIN

Figure 70. CFx Pin Recommended Connection

Synchronizing Energy Registers with CFx Outputs

The ADE7878 contains a feature that allows synchronizing the

content of phase energy accumulation registers with the

generation of a CFx pulse. When a high-to-low transition at one

frequency converter output occurs, the content of all internal

phase energy registers that relate to the power being output at

CFx pin is latched into hour registers and then resets to 0. See

Table 21 for the list of registers that are latched based on the

CFxSEL[2:0] bits in the CFMODE[15:0] register. All 3-phase

registers are latched independent of the TERMSELx bits of the

COMPMODE[15:0] register. The process is shown in Figure 71

for CF1SEL[2:0] = 010 (apparent powers contribute at the CF1

pin) and CFCYC = 2.

The CFCYC[7:0] 8-bit unsigned register contains the number of

high-to-low transitions at the frequency converter output

between two consecutive latches. Writing a new value into the

CFCYC[7:0] register during a high-to-low transition at any CFx

pin should be avoided.

CFCYC = 2

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

AVAHR, BVAHR,

CVAHR LATCHED

ENERGY REGISTERS

RESET

CF1 PULSE

BASED ON

PHASE A AND

PHASE B

APPARENT

POWERS

Figure 71. Synchronizing AVAHR and BVAHR with CF1

Bits[14:12] (CF3LATCH, CF2LATCH and CF1LATCH) of the

CFMODE[15:0] register enable this process when set to 1.

When cleared to 0, the default state, no latch occurs. The

process is available even if the CFx output is not enabled by the

CFxDIS bits in the CFMODE[15:0] register.

CF Outputs for Various Accumulation Modes

Bits[1:0] (WATTACC[1:0]) in the ACCMODE[7:0] register

determine the accumulation modes of the total active and

fundamental powers when signals proportional to the active

powers are chosen at the CFx pins (Bit CFxSEL[2:0] in the

CFMODE[15:0] register equals 000 or 011). When

WATTACC[1:0] = 00 (the default value), the active powers are

sign accumulated before entering the energy-to-frequency

converter. Figure 72 shows how signed active power

accumulation works. Note that in this mode, the CFx pulses are

synchronized perfectly with the active energy accumulated in

xWATTHR registers because the powers are sign accumulated

in both datapaths.

NEG

POS

APNOLOAD

SIGN = POSITIVE

NEG

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

ACTIVE ENERGY

REVAPx BIT

IN STATUS0

xWSIGN BIT

IN PHSIGN

Figure 72. Active Power Signed Accumulation Mode

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