ADE7878ACPZ datasheet(88/92 Pages) AD

88 / 92 page

ADE7878

Rev. 0| Page 88 of 92

Table 45. CONSEL[1:0] Bits in Energy Registers

Energy Registers

CONSEL[1:0]=00

CONSEL[1:0]=01

CONSEL[1:0]=10

CONSEL[1:0]=11

AWATTHR, AFWATTHR

VA × IA

BWATTHR, BFWATTHR

VB × IB

VB = −VA − VC

VB = −VA

VB × IB

CWATTHR, CFWATTHR

VC × IC

VC x IC

VC × IC

AVARHR, AFVARHR

VA × IA’

VA x IA’

VA × IA’

BVARHR, BFVARHR

VB × IB’

VB = −VA − VC

VB = −VA

VB × IB’

CVARHR, CFVARHR

VC ×IC’

VC × IC’

AVAHR

VA rms × IA rms

BVAHR

VB rms × IB rms

CVAHR

VC rms × IC rms

Table 46. LCYCMODE Register (Address 0xE702)

Bit

Location

Bit Name

Default Value

Description

LWATT

0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR,

and CFWATTHR) are placed in regular accumulation mode.

1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR,

and CFWATTHR) are placed into line-cycle accumulation mode.

LVAR

0: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed in regular

accumulation mode.

1: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed into line-cycle

accumulation mode.

LVA

0: the VA-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed in regular

accumulation mode.

1: the VA-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed into line-cycle

accumulation mode.

ZXSEL[0]

0: Phase A is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase A is selected for zero-crossings counts in the line cycle accumulation mode. If more than

one phase is selected for zero-crossing detection, the accumulation time is shortened accordingly.

ZXSEL[1]

0: Phase B is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase B is selected for zero-crossings counts in the line cycle accumulation mode.

ZXSEL[2]

0: Phase C is not selected for zero-crossings counts in the line cycle accumulation mode.

1: Phase C is selected for zero-crossings counts in the line cycle accumulation mode.

RSTREAD

0: read-with-reset of all energy registers is disabled. Clear this bit to 0 when Bits[2:0] (LWATT,

LVAR, LVA) are set to 1.

1: enables read-with-reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers.

This means that a read of those registers resets them to 0.

Reserved

Reserved. This bit does not manage any functionality.

Table 47. HSDC_CFG Register (Address 0xE706)

Bit Location

Bit Name

Default Value

Description

HCLK

0: HSCLK is 8 MHz.

1: HSCLK is 4 MHz.

HSIZE

0: HSDC transmits the 32-bit registers in 32-bit packages, most significant bit first.

1: HSDC transmits the 32-bit registers in 8-bit packages, most significant bit first.

HGAP

0: no gap is introduced between packages.

1: a gap of seven HCLK cycles is introduced between packages.

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