ADE7878ACPZ datasheet(66/92 Pages) AD

66 / 92 page

ADE7878

Rev. 0 | Page 66 of 92

15 14

SCLK

MOSI

MISO

31 30

000

Figure 83. SPI Read Operation of a 32-Bit Register

15 14

SCLK

MOSI

10 31 30

000

Figure 84. SPI Write Operation of a 32-Bit Register

HSDC is an interface that is used to send to an external device,

usually a microprocessor or a DSP, up to sixteen 32-bit words.

The words represent the instantaneous values of the phase currents

and voltages, neutral current, and active, reactive, and apparent

powers. The registers being transmitted are: IAWV[23:0],

VAWV[23:0], IBWV[23:0], VBWV[23:0], ICWV[23:0],

VCWV[23:0], AVA[23:0], INWV[23:0], BVA[23:0], CVA[23:0],

AWATT[23:0], BWATT[23:0], CWATT[23:0], AVAR[23:0],

BVAR[23:0], and CVAR[23:0]. All are 24-bit registers that are

sign extended to 32-bits (see Figure 34 for details). HSDC can

be interfaced with SPI or similar interfaces.

HSDC is always a master of the communication and consists of

three pins: HSA, HSD, and HSCLK. HSA represents the select

signal. It stays active low or high when a word is transmitted

and is usually connected to the select pin of the slave. HSD is

used to send data to the slave and is usually connected to the

data input pin of the slave. HSCLK is the serial clock line. It is

generated by the ADE7878 and is usually connected to the serial

clock input of the slave. Figure 85 presents the connections

between the ADE7878 HSDC and slave devices containing an

SPI interface.

The HSDC communication is managed by the HSDC_CFG[7:0]

(HSDCEN) in the CONFIG[15:0] register. In this way, the state of

various pins belonging to the HSDC port do not take levels incon-

sistent with the desired HSDC behavior. After a hardware reset

or after power-up, the MISO/HSD and SS/HSA pins are set high.

Bit 0 (HCLK) in the HSDC_CFG[7:0] register determines the

serial clock frequency of the HSDC communication. When

HCLK is 0 (the default value), the clock frequency is 8 MHz.

When HCLK is 1, the clock frequency is 4 MHz. A bit of data is

transmitted for every HSCLK high-to-low transition. The slave

device that receives data from HSDC samples the HSD line on

the low-to-high transition of HSCLK.

HSD

HSCLK

HSA

ADE7878

MOSI

SCK

SPI DEVICE

Figure 85. Connecting the ADE7878 HSDC with an SPI

The words can be transmitted as 32-bit packages or as 8-bit

packages. When Bit 1 (HSIZE) in the HSDC_CFG[7:0] register is 0

(the default value), the words are transmitted as 32-bit packages.

When Bit HSIZE is 1, the registers are transmitted as 8-bit pack-

ages. The HSDC interface transmits the words MSB first.

Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between

packages, when Bit 2 (HGAP) is set to 1. When Bit HGAP is

cleared to 0 (the default value), no gap is introduced between

packages and the communication time is shortest. In this case,

HSIZE does not have any influence on the communication, and

a bit is put on the HSD line every HSCLK high-to-low transition.

Bits[4:3] (HXFER[1:0]) decide how many words are

transmitted. When HXFER[1:0] is 00, the default value, then all

16 words are transmitted. When HXFER[1:0] is 01, only the

words representing the instantaneous values of the phase and

neutral currents and phase voltages are transmitted in the

following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV,

and one 32-bit word that is always equal to INWV.

ADE7878ACPZ Datasheet(PDF) 66 Page - Analog Devices

ADE7878ACPZ Datasheet(HTML) 66 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL