T108 Release
Copyright by Terawins, Inc.
45
3.2 Input Timing Register Set
3.2.1
De-Interlaced Process & Vertical Shadow Control Register
Address Offset:
30h
Access:
Read/Write
Default Value:
82h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
RO
Reserved
[5]
R/W
VST_CHGSEL
1:Vsync timing change determined by 8*# of XCLK
0:Vsync timing change determined by # of hsync (default)
# can be assigned at Reg 0x3A
[4]
R/W
INT_EDGE
Interrupt polarity
1: positive
0: negative (default)
[3]
R/W
LB_SIZE_FIXED
This bit control capture size for Scaler.
1: Hsize and Vsize are assigned by 54h ~57h
0: sizes assigned by input sources. (default)
[2]
R/W
ENQKHS
Reserved for chip teset only, set to 0 for normal operation
[1]
R/W
ITLCPRO
Set 1 for interlaced video (default)
Set 0 for non-interlaced video
[0]
R/W
ADC_Odd_in_HsVs
Set to 1 for enabling detecting Odd flag from HS/VS pins
3.2.2
Source Select Register
Address Offset:
31h
Access:
Read/Write
Default Value:
04h
Size:
8 bits
Bit
Access
Symbol
Description
[7]
RO
ITLCFLM
Indicates incoming video signal is interlaced if get 1
[6:4]
R/W
VIP_Sel[2:0]
Select the digital input source (VIP: Video Input):
000: A656
001: B656
010: L601_8bits
011: L601_16bits
100: Reserved
101: RGB565
110: RGB666
111: RGB888
[3:2]
R/W
InSource_Sel[1:0]
Select the input source:
00: Digital VIP input
01: select VD input (CVBS, S-Video, YPbPr)
10: Select ADC RGB, SOY(YPbPr)
11: Reserved
[1]
RO
Reserved
[0]
RO
VBI_Field
Current VBI field information
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