49 / 89 page
T108 Release
Copyright by Terawins, Inc.
49
3.2.17
ADC Capture Control Register
Address Offset:
47h
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7]
R/W
Mask_H_Left
Set to 1 for mask left portion when wrap.
[6]
R/W
Mask_H_Right
Set to 1 for mask right portion when wrap.
[5]
R/W
Mask_V_Top
Set to 1 for mask top portion when wrap.
[4]
R/W
Mask_V_Bottom
Set to 1 for mask bottom portion when wrap.
[3:1]
RO
Reserved
[0]
R/W
Reserved
Reserved for chip test only
3.2.18
ADC Capture HSize LSB Register
Address Offset:
48h
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
ADC_HSize[7:0]
ADC Capture window: Horizontal Size (# dots).
3.2.19
ADC Capture HSize MSB Register
Address Offset:
49h
Access:
Read/Write
Default Value:
02h
Size:
8 bits
Bit
Access
Symbol
Description
[7:3]
RO
Reserved
[2:0]
R/W
ADC_HSize[10:8]
ADC Capture window: Horizontal Size (# dots).
3.2.20
ADC Capture VSize LSB Register
Address Offset:
4Ah
Access:
Read/Write
Default Value:
E0h
Size:
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
ADC_VSize[7:0]
ADC Capture window: Vertical Size (# lines).
3.2.21
ADC Capture VSize MSB Register
Address Offset:
4Bh
Access:
Read/Write
Default Value:
01h
Size:
8 bits
Bit
Access
Symbol
Description
[7:2]
RO
Reserved
[1:0]
R/W
ADC_VSize[9:8]
ADC Capture window: Vertical Size (# lines).
3.2.22
ADC Capture HSync Back Porch LSB Register
Address Offset:
4Ch
Access:
Read/Write
Default Value:
10h
Size:
8 bits
Bit
Access
Symbol
Description
[7:0]
R/W
ADC_HStart[7:0]
ADC Capture window: HSync Start Point (# dots).
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