HT45R37 datasheet(48/100 Pages) HOLTEK

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HT45R37

Rev. 1.10

January 29, 2010

Step 2

Set the SIMEN bit in the SIMCTL0 register to

²1² to en-

able the I

2C bus.

Step 3

Set the ESIM and EMFI0 bits of the interrupt control

2C bus interrupt.

· Start Signal

The START signal can only be generated by the mas-

ter device connected to the I

2C bus and not by the

microcontroller, which is only a slave device. This

START signal will be detected by all devices con-

nected to the I

2C bus. When detected, this indicates

that the I

2C bus is busy and therefore the HBB bit will

be set. A START condition occurs when a high to low

transition on the SDA line takes place when the SCL

line remains high.

· Slave Address

The transmission of a START signal by the master will

be detected by all devices on the I

2C bus. To deter-

mine which slave device the master wishes to com-

municate with, the address of the slave device will be

sent out immediately following the START signal. All

slave devices, after receiving this 7-bit address data,

will compare it with their own 7-bit slave address. If the

address sent out by the master matches the internal

address of the microcontroller slave device, then an

internal I

2C bus interrupt signal will be generated. The

next bit following the address, which is the 8th bit, de-

fines the read/write status and will be saved to the

SRW bit of the SIMCTL1 register. The device will then

transmit an acknowledge bit, which is a low level, as

the 9th bit. The microcontroller slave device will also

set the status flag HAAS when the addresses match.

As an I

2C bus interrupt can come from two sources,

when the program enters the interrupt subroutine, the

HAAS bit should be examined to see whether the in-

terrupt source has come from a matching slave ad-

dress or from the completion of a data byte transfer.

When a slave address is matched, the device must be

placed in either the transmit mode and then write data

to the SIMDR register, or in the receive mode where it

must implement a dummy read from the SIMDR regis-

ter to release the SCL line.

· SRW Bit

The SRW bit in the SIMCTL1 register defines whether

the microcontroller slave device wishes to read data

from the I

2C bus or write data to the I2C bus. The

microcontroller should examine this bit to determine if

it is to be a transmitter or a receiver. If the SRW bit is

set to

²1² then this indicates that the master wishes to

read data from the I

2 C bus, therefore the

microcontroller slave device must be setup to send

data to the I

2C bus as a transmitter. If the SRW bit is

²0² then this indicates that the master wishes to send

data to the I

2C bus, therefore the microcontroller slave

device must be setup to read data from the I

2C bus as

a receiver.

· Acknowledge Bit

After the master has transmitted a calling address,

any slave device on the I

2C bus, whose own internal

address matches the calling address, must generate

an acknowledge signal. This acknowledge signal will

inform the master that a slave device has accepted its

calling address. If no acknowledge signal is received

by the master then a STOP signal must be transmitted

by the master to end the communication. When the

HAAS bit is high, the addresses have matched and

the microcontroller slave device must check the SRW

bit to determine if it is to be a transmitter or a receiver.

If the SRW bit is high, the microcontroller slave device

should be setup to be a transmitter so the HTX bit in

the SIMCTL1 register should be set to

²1² if the SRW

bit is low then the microcontroller slave device should

be setup as a receiver and the HTX bit in the SIMCTL1

²0².

· Data Byte

The transmitted data is 8-bits wide and is transmitted

after the slave device has acknowledged receipt of its

slave address. The order of serial bit transmission is

the MSB first and the LSB last. After receipt of 8-bits of

data, the receiver must transmit an acknowledge sig-

nal, level

²0², before it can receive the next data byte.

If the transmitter does not receive an acknowledge bit

signal from the receiver, then it will release the SDA

line and the master will send out a STOP signal to re-

lease control of the I

2C bus. The corresponding data

will be stored in the SIMDR register. If setup as a

transmitter, the microcontroller slave device must first

write the data to be transmitted into the SIMDR regis-

ter. If setup as a receiver, the microcontroller slave de-

vice must read the transmitted data from the SIMDR

· Receive Acknowledge Bit

When the receiver wishes to continue to receive the

next data byte, it must generate an acknowledge bit,

known as TXAK, on the 9th clock. The microcontroller

slave device, which is setup as a transmitter will check

the RXAK bit in the SIMCTL1 register to determine if it

is to send another data byte, if not then it will release

the SDA line and await the receipt of a STOP signal

from the master.

S C L

S D A

S t a r t b i t

D a t a

s t a b l e

D a t a

a l l o w

c h a n g e

S t o p b i t

Data Timing Diagram

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