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HT45R37 Datasheet(PDF) 64 Page - Holtek Semiconductor Inc |
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HT45R37 Datasheet(HTML) 64 Page - Holtek Semiconductor Inc |
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64 / 100 page ![]() HT45R37 Rev. 1.10 64 January 29, 2010 gether with fSYS/4, it is used as a clock source for certain internal functions such as the Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The internal clock fS, is simply a choice of either fSUB or fSYS/4, using a configuration option. Operating Modes After the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the CLKMOD register and use of the HALT instruction determine in which mode the device will be run. The devices can operate in the follow- ing Modes. · Normal mode fM on, fSLOW on, fSYS=fM, CPU on, fS on, fWDT on/off de- pending upon the WDT configuration option and WDT control register. · Slow mode0 fM off, fSLOW=32K_INT oscillator or the 32768Hz oscil- lator, fSYS=fSLOW, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. · Slow mode1 fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. · Idle mode fM,fSLOW,fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS/4, fWDT on/off depending upon the WDT configuration option and WDT control register. · Sleep mode fM,fSLOW,fSYS,fS, CPU off; fSUB,fWDT on/off depending upon the WDT configuration option and WDT control register. Switching Between Modes The device switches between the different operating modes using a combination of the HALT instruction and the IDLEN bit in the CLKMOD register. Switching to one of the lower power modes enables the normal operating current to be reduced to a lower operating level or to a very low standby current level, a feature which is very important in low power battery applications. C L K M O D R e g i s t e r f S Y S s e l e c t 1 : f M 0 : f S L O W I d l e m o d e 1 : e n a b l e 0 : d i s a b l e H i g h o s c i l l a t o r r e a d y f l a g 1 : t i m e - o u t 0 : n o n - t i m e - o u t L o w o s c i l l a t o r r e a d y f l a g 1 : t i m e - o u t 0 : n o n - t i m e - o u t S P I / I C c o n t i n u e s r u n n i n g i n I d l e m o d e 1 : e n a b l e 0 : d i s a b l e f S L O W s e l e c t i o n b 0 I D L E N H L C L K H T O L T O b 7 S L O W C 0 S L O W C 1 S L O W C 2 f S L O W f S L f S L f M / 6 4 f M / 3 2 f M / 1 6 f M / 8 f M / 4 f M / 2 S L O W W C 2 0 0 0 0 1 1 1 1 S L O W W C 1 0 0 1 1 0 0 1 1 S L O W W C 0 0 1 0 1 0 1 0 1 S I M I D L E 2 Clock Control Register - CLKMOD |
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