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AM1808AZCED3 Datasheet(PDF) 107 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 107 Page - Texas Instruments |
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107 / 264 page  AM1808 www.ti.com SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 6.11 DDR2/mDDR Controller The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. The DDR2/mDDR Memory Controller support the following features: • JESD79-2A standard compliant DDR2 SDRAM • Mobile DDR SDRAM • 512 MByte memory space for DDR2 • 256 MByte memory space for mDDR • CAS latencies: – DDR2: 2, 3, 4 and 5 – mDDR: 2 and 3 • Internal banks: – DDR2: 1, 2, 4 and 8 – mDDR:1, 2 and 4 • Burst length: 8 • Burst type: sequential • 1 chip select (CS) signal • Page sizes: 256, 512, 1024 and 2048 • SDRAM autoinitialization • Self-refresh mode • Partial array self-refresh (for mDDR) • Power down mode • Prioritized refresh • Programmable refresh rate and backlog counter • Programmable timing parameters • Little endian 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing Table 6-23. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR Memory Controller No. PARAMETER 1.3V 1.2V 1.1V 1.0V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 72 degree DLL 125 150 125 150 125 150 —(1) —(1) configuration DDR2 90 degree DLL Cycle time, 125 150 125 150 125 150 —(1) —(1) configuration DDR_CLKP 1 tc(DDR_CLK) MHz / 72 degree DLL 90 150 90 133 75 133 65 133 DDR_CLKN configuration mDDR 90 degree DLL 105 133 105 133 100 133 95 133 configuration (1) DDR2 is not supported at this voltage operating point. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 107 Submit Documentation Feedback Product Folder Link(s): AM1808 |
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