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AM1808AZCED3 Datasheet(PDF) 118 Page - Texas Instruments |
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AM1808AZCED3 Datasheet(HTML) 118 Page - Texas Instruments |
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118 / 264 page  A1 A1 E0 T E1 T AM1808 SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010 www.ti.com Figure 6-22 shows the topology and routing for the DQS and DQ net class; the routes are point to point. Skew matching across bytes is not needed nor recommended. Figure 6-22. DQS and DQ Routing and Topology Table 6-35. DQS and DQ Routing Specification No. Parameter Min Typ Max Unit Notes 1 DQS E Skew Length Mismatch 25 Mils 2 Center to center DQS to other DDR2/mDDR trace 4w (1) See Note (2) spacing 3 DQS/D nominal trace length DQLM-50 DQLM DQLM+50 Mils See Notes (3), (4) 4 D to DQS Skew Length Mismatch 100 Mils See Note (4) 5 D to D Skew Length Mismatch 100 Mils See Note (4) 6 Center to center D to other DDR2/mDDR trace 4w (1) See Notes (2), (5) spacing 7 Center to Center D to other D trace spacing 3w (1) See Notes (6), (2) 8 DQ/DQS E Skew Length Mismatch 100 Mils See Note (4) (1) w = PCB trace width as defined in Table 6-27 . (2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. (3) Series terminator, if used, should be located closest to DDR. (4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1. (5) D's from other DQS domains are considered other DDR2/mDDR trace. (6) DQLM is the longest Manhattan distance of each of the DQS and D net class. 118 Peripheral Information and Electrical Specifications Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
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