AM1808AZCED3 datasheet(115/264 Pages) TI

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AM1808

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SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

6.11.3.8 Net Classes

Table 6-31 lists the clock net classes for the DDR2/mDDR interface. Table 6-32 lists the signal net

classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes

are used for the termination and routing rules that follow.

Table 6-31. Clock Net Class Definitions

Clock Net Class

Pin Names

DDR_CLKP / DDR_CLKN

DQS0

DDR_DQS[0]

DQS1

DDR_DQS[1]

Table 6-32. Signal Net Class Definitions

Associated Clock Net

Clock Net Class

Class

Pin Names

ADDR_CTRL

DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,

DDR_CKE

DQS0

DDR_D[7:0], DDR_DQM0

DQS1

DDR_D[15:8], DDR_DQM1

DQGATE

CK, DQS0, DQS1

DDR_DQGATE0, DDR_DQGATE1

6.11.3.9 DDR2/mDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only

type permitted. Table 6-33 shows the specifications for the series terminators.

Table 6-33. DDR2/mDDR Signal Terminations

No.

Parameter

Min

Typ

Max

Unit

Notes

CK Net Class

Ω

See Note (1)

ADDR_CTRL Net Class

Ω

See Notes (1), (2), (3)

Data Byte Net Classes (DQS[0], DQS[1], D0, D1)

Ω

See Notes (1), (2), (3), (4)

DQGATE Net Class (DQGATE)

Ω

See Notes (1), (2), (3)

(1)

Only series termination is permitted, parallel or SST specifically disallowed.

(2)

Terminator values larger than typical only recommended to address EMI issues.

(3)

Termination value should be uniform across net class.

(4)

When no termination is used on data lines (0

Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.

Peripheral Information and Electrical Specifications

115

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