AM1808AZCED3 datasheet(150/264 Pages) TI

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Peripheral

Configuration Bus

Interrupt and

DMA Requests

16-Bit Shift Register

16-Bit Buffer

GPIO

Control

(all pins)

State

Machine

Clock

Control

SPIx_SIMO

SPIx_SOMI

SPIx_ENA

SPIx_SCS

SPIx_CLK

AM1808

SPRS653A – FEBRUARY 2010 – REVISED APRIL 2010

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6.17 Serial Peripheral Interface Ports (SPI0, SPI1)

Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control

logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end

of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives

the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many

data formatting options.

Figure 6-34. Block Diagram of SPI Module

The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and

SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).

The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are

other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin

when SPIx_SCS is held low.

In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain

manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In

four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating

that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified

by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the

same SPI bus.

In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start

of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI

communications and, on average, increases SPI bus throughput since the master does not need to delay

each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer

can begin as soon as both the master and slave have actually serviced the previous SPI transfer.

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Peripheral Information and Electrical Specifications

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